coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-only */
2
3
#include <baseboard/gpio.h>
4
#include <baseboard/variants.h>
5
#include <
commonlib/helpers.h
>
6
7
static
const
struct
pad_config
gpio_table
[] = {
8
/* A17 : SD_VDD1_PWR_EN */
9
PAD_NC
(
GPP_A17
,
NONE
),
10
/* A18 : GPP_A18 */
11
PAD_NC
(
GPP_A18
,
NONE
),
12
/* A19 : GPP_A19 */
13
PAD_NC
(
GPP_A19
,
NONE
),
14
/* A20 : TOUCH_INT_ODL */
15
PAD_CFG_GPI_IRQ_WAKE(
GPP_A20
,
NONE
, PLTRST, LEVEL, INVERT),
16
/* A21 : FPMCU_PCH_BOOT0 */
17
PAD_NC
(
GPP_A21
,
NONE
),
18
/* A22 : FPMCU_PCH_INT_L */
19
PAD_NC
(
GPP_A22
,
NONE
),
20
/* A23 : M2_WLAN_INT_ODL */
21
PAD_CFG_GPI_APIC
(
GPP_A23
,
NONE
, PLTRST, LEVEL, INVERT),
22
23
/* C0 : SMBCLK */
24
PAD_CFG_NF
(
GPP_C0
,
NONE
, DEEP, NF1),
25
/* C1 : SMBDATA */
26
PAD_CFG_NF
(
GPP_C1
,
NONE
, DEEP, NF1),
27
/* C3 : GPP_C3 */
28
PAD_NC
(
GPP_C3
,
NONE
),
29
/* C4 : GPP_C4 */
30
PAD_NC
(
GPP_C4
,
NONE
),
31
/* C6: M2_WLAN_WAKE_ODL */
32
PAD_CFG_GPI_SCI_LOW
(
GPP_C6
,
NONE
, DEEP, EDGE_SINGLE),
33
/* C7 : LAN_WAKE_ODL */
34
PAD_NC
(
GPP_C7
,
NONE
),
35
/* C11 : GPP_C11 */
36
PAD_NC
(
GPP_C11
,
NONE
),
37
/* C15 : WLAN_OFF_L */
38
PAD_CFG_GPO
(
GPP_C15
, 1, DEEP),
39
/* C18 : GPP_C18 */
40
PAD_NC
(
GPP_C18
,
NONE
),
41
/* C19 : GPP_C19 */
42
PAD_NC
(
GPP_C19
,
NONE
),
43
44
/* D16 : DMIC_ON_OFF MIC_SWITCH_L */
45
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_D16
,
NONE
, DEEP),
46
47
/* E2 : EN_PP_MST_OD */
48
PAD_CFG_GPO
(
GPP_E2
, 1, DEEP),
49
50
/* F0 : GPP_F0 */
51
PAD_NC
(
GPP_F0
,
NONE
),
52
/* F1 : GPP_F1 */
53
PAD_NC
(
GPP_F1
,
NONE
),
54
/* F8 : GPP_F8 */
55
PAD_NC
(
GPP_F8
,
NONE
),
56
/* F9 : GPP_F9 */
57
PAD_NC
(
GPP_F9
,
NONE
),
58
/* F11 : EMMC_CMD */
59
PAD_CFG_NF
(
GPP_F11
,
NONE
, DEEP, NF1),
60
/* F12 : EMMC_DATA0 */
61
PAD_CFG_NF
(
GPP_F12
,
NONE
, DEEP, NF1),
62
/* F13 : EMMC_DATA1 */
63
PAD_CFG_NF
(
GPP_F13
,
NONE
, DEEP, NF1),
64
/* F14 : EMMC_DATA2 */
65
PAD_CFG_NF
(
GPP_F14
,
NONE
, DEEP, NF1),
66
/* F15 : EMMC_DATA3 */
67
PAD_CFG_NF
(
GPP_F15
,
NONE
, DEEP, NF1),
68
/* F16 : EMMC_DATA4 */
69
PAD_CFG_NF
(
GPP_F16
,
NONE
, DEEP, NF1),
70
/* F17 : EMMC_DATA5 */
71
PAD_CFG_NF
(
GPP_F17
,
NONE
, DEEP, NF1),
72
/* F18 : EMMC_DATA6 */
73
PAD_CFG_NF
(
GPP_F18
,
NONE
, DEEP, NF1),
74
/* F19 : EMMC_DATA7 */
75
PAD_CFG_NF
(
GPP_F19
,
NONE
, DEEP, NF1),
76
/* F20 : EMMC_RCLK */
77
PAD_CFG_NF
(
GPP_F20
,
NONE
, DEEP, NF1),
78
/* F21 : EMMC_CLK */
79
PAD_CFG_NF
(
GPP_F21
,
NONE
, DEEP, NF1),
80
/* F22 : EMMC_RST_L */
81
PAD_CFG_NF
(
GPP_F22
,
NONE
, DEEP, NF1),
82
83
/* G0 : SD_CMD */
84
PAD_NC
(
GPP_G0
,
NONE
),
85
/* G1 : SD_DATA0 */
86
PAD_NC
(
GPP_G1
,
NONE
),
87
/* G2 : SD_DATA1 */
88
PAD_NC
(
GPP_G2
,
NONE
),
89
/* G3 : SD_DATA2 */
90
PAD_NC
(
GPP_G3
,
NONE
),
91
/* G4 : SD_DATA3 */
92
PAD_NC
(
GPP_G4
,
NONE
),
93
/* G5 : SD_CD */
94
PAD_NC
(
GPP_G5
,
NONE
),
95
/* G6 : SD_CLK */
96
PAD_NC
(
GPP_G6
,
NONE
),
97
98
/* H3 : SPK_AMP_ON */
99
PAD_CFG_GPO
(
GPP_H3
, 1, DEEP),
100
/* H4: LVDS_SDA */
101
PAD_CFG_NF
(
GPP_H4
,
NONE
, DEEP, NF1),
102
/* H5: LVDS_SDL */
103
PAD_CFG_NF
(
GPP_H5
,
NONE
, DEEP, NF1),
104
/* H6 : PCH_I2C_TOUCH_SDA */
105
PAD_CFG_NF
(
GPP_H6
,
NONE
, DEEP, NF1),
106
/* H7 : PCH_I2C_TOUCH_SDL */
107
PAD_CFG_NF
(
GPP_H7
,
NONE
, DEEP, NF1),
108
};
109
110
const
struct
pad_config
*
override_gpio_table
(
size_t
*num)
111
{
112
*num =
ARRAY_SIZE
(
gpio_table
);
113
return
gpio_table
;
114
}
115
116
/* Early pad configuration in bootblock */
117
static
const
struct
pad_config
early_gpio_table
[] = {
118
/* B14 : GPP_B14_STRAP */
119
PAD_NC
(
GPP_B14
,
NONE
),
120
/* B22 : GPP_B22_STRAP */
121
PAD_NC
(
GPP_B22
,
NONE
),
122
/* E19 : GPP_E19_STRAP */
123
PAD_NC
(
GPP_E19
,
NONE
),
124
/* E21 : GPP_E21_STRAP */
125
PAD_NC
(
GPP_E21
,
NONE
),
126
/* B15 : H1_SLAVE_SPI_CS_L */
127
PAD_CFG_NF
(
GPP_B15
,
NONE
, DEEP, NF1),
128
/* B16 : H1_SLAVE_SPI_CLK */
129
PAD_CFG_NF
(
GPP_B16
,
NONE
, DEEP, NF1),
130
/* B17 : H1_SLAVE_SPI_MISO_R */
131
PAD_CFG_NF
(
GPP_B17
,
NONE
, DEEP, NF1),
132
/* B18 : H1_SLAVE_SPI_MOSI_R */
133
PAD_CFG_NF
(
GPP_B18
,
NONE
, DEEP, NF1),
134
/* C14 : BT_DISABLE_L */
135
PAD_CFG_GPO
(
GPP_C14
, 0, DEEP),
136
/* PCH_WP_OD */
137
PAD_CFG_GPI
(
GPP_C20
,
NONE
, DEEP),
138
/* C21 : H1_PCH_INT_ODL */
139
PAD_CFG_GPI_APIC
(
GPP_C21
,
NONE
, PLTRST, LEVEL, INVERT),
140
/* C22 : EC_IN_RW_OD */
141
PAD_CFG_GPI
(
GPP_C22
,
NONE
, DEEP),
142
/* C23 : WLAN_PE_RST# */
143
PAD_CFG_GPO
(
GPP_C23
, 1, DEEP),
144
/* E1 : M2_SSD_PEDET */
145
PAD_CFG_NF
(
GPP_E1
,
NONE
, DEEP, NF1),
146
/* E5 : SATA_DEVSLP1 */
147
PAD_CFG_NF
(
GPP_E5
,
NONE
, PLTRST, NF1),
148
};
149
150
const
struct
pad_config
*
variant_early_gpio_table
(
size_t
*num)
151
{
152
*num =
ARRAY_SIZE
(
early_gpio_table
);
153
return
early_gpio_table
;
154
}
GPP_C15
#define GPP_C15
Definition:
gpio_soc_defs.h:552
GPP_A18
#define GPP_A18
Definition:
gpio_soc_defs.h:137
GPP_F21
#define GPP_F21
Definition:
gpio_soc_defs.h:594
GPP_F12
#define GPP_F12
Definition:
gpio_soc_defs.h:585
GPP_F16
#define GPP_F16
Definition:
gpio_soc_defs.h:589
GPP_F20
#define GPP_F20
Definition:
gpio_soc_defs.h:593
GPP_B16
#define GPP_B16
Definition:
gpio_soc_defs.h:69
GPP_F0
#define GPP_F0
Definition:
gpio_soc_defs.h:573
GPP_A19
#define GPP_A19
Definition:
gpio_soc_defs.h:138
GPP_H6
#define GPP_H6
Definition:
gpio_soc_defs.h:222
GPP_C22
#define GPP_C22
Definition:
gpio_soc_defs.h:559
GPP_B15
#define GPP_B15
Definition:
gpio_soc_defs.h:68
GPP_C23
#define GPP_C23
Definition:
gpio_soc_defs.h:560
GPP_H7
#define GPP_H7
Definition:
gpio_soc_defs.h:223
GPP_C11
#define GPP_C11
Definition:
gpio_soc_defs.h:548
GPP_B22
#define GPP_B22
Definition:
gpio_soc_defs.h:75
GPP_A23
#define GPP_A23
Definition:
gpio_soc_defs.h:142
GPP_C18
#define GPP_C18
Definition:
gpio_soc_defs.h:555
GPP_F9
#define GPP_F9
Definition:
gpio_soc_defs.h:582
GPP_E5
#define GPP_E5
Definition:
gpio_soc_defs.h:633
GPP_C20
#define GPP_C20
Definition:
gpio_soc_defs.h:557
GPP_A20
#define GPP_A20
Definition:
gpio_soc_defs.h:139
GPP_F1
#define GPP_F1
Definition:
gpio_soc_defs.h:574
GPP_F17
#define GPP_F17
Definition:
gpio_soc_defs.h:590
GPP_F15
#define GPP_F15
Definition:
gpio_soc_defs.h:588
GPP_C6
#define GPP_C6
Definition:
gpio_soc_defs.h:543
GPP_F13
#define GPP_F13
Definition:
gpio_soc_defs.h:586
GPP_C4
#define GPP_C4
Definition:
gpio_soc_defs.h:541
GPP_E2
#define GPP_E2
Definition:
gpio_soc_defs.h:630
GPP_E19
#define GPP_E19
Definition:
gpio_soc_defs.h:647
GPP_H5
#define GPP_H5
Definition:
gpio_soc_defs.h:221
GPP_C21
#define GPP_C21
Definition:
gpio_soc_defs.h:558
GPP_F14
#define GPP_F14
Definition:
gpio_soc_defs.h:587
GPP_H3
#define GPP_H3
Definition:
gpio_soc_defs.h:219
GPP_B14
#define GPP_B14
Definition:
gpio_soc_defs.h:67
GPP_B18
#define GPP_B18
Definition:
gpio_soc_defs.h:71
GPP_C14
#define GPP_C14
Definition:
gpio_soc_defs.h:551
GPP_F8
#define GPP_F8
Definition:
gpio_soc_defs.h:581
GPP_C19
#define GPP_C19
Definition:
gpio_soc_defs.h:556
GPP_A21
#define GPP_A21
Definition:
gpio_soc_defs.h:140
GPP_C1
#define GPP_C1
Definition:
gpio_soc_defs.h:538
GPP_F18
#define GPP_F18
Definition:
gpio_soc_defs.h:591
GPP_A22
#define GPP_A22
Definition:
gpio_soc_defs.h:141
GPP_F22
#define GPP_F22
Definition:
gpio_soc_defs.h:595
GPP_F11
#define GPP_F11
Definition:
gpio_soc_defs.h:584
GPP_D16
#define GPP_D16
Definition:
gpio_soc_defs.h:268
GPP_E21
#define GPP_E21
Definition:
gpio_soc_defs.h:649
GPP_C3
#define GPP_C3
Definition:
gpio_soc_defs.h:540
GPP_A17
#define GPP_A17
Definition:
gpio_soc_defs.h:136
GPP_B17
#define GPP_B17
Definition:
gpio_soc_defs.h:70
GPP_C0
#define GPP_C0
Definition:
gpio_soc_defs.h:537
GPP_E1
#define GPP_E1
Definition:
gpio_soc_defs.h:629
GPP_F19
#define GPP_F19
Definition:
gpio_soc_defs.h:592
GPP_H4
#define GPP_H4
Definition:
gpio_soc_defs.h:220
GPP_C7
#define GPP_C7
Definition:
gpio_soc_defs.h:544
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
GPP_G1
#define GPP_G1
Definition:
gpio_soc_defs.h:89
GPP_G4
#define GPP_G4
Definition:
gpio_soc_defs.h:92
GPP_G2
#define GPP_G2
Definition:
gpio_soc_defs.h:90
GPP_G6
#define GPP_G6
Definition:
gpio_soc_defs.h:94
GPP_G0
#define GPP_G0
Definition:
gpio_soc_defs.h:88
GPP_G3
#define GPP_G3
Definition:
gpio_soc_defs.h:91
GPP_G5
#define GPP_G5
Definition:
gpio_soc_defs.h:93
helpers.h
variant_early_gpio_table
const struct pad_config * variant_early_gpio_table(size_t *num)
Definition:
gpio.c:204
override_gpio_table
const struct pad_config * override_gpio_table(size_t *num)
Definition:
gpio.c:124
gpio_table
static const struct pad_config gpio_table[]
Definition:
gpio.c:7
early_gpio_table
static const struct pad_config early_gpio_table[]
Definition:
gpio.c:117
NONE
@ NONE
Definition:
qup_se_handlers_common.h:196
PAD_NC
#define PAD_NC(pin)
Definition:
gpio_defs.h:263
PAD_CFG_GPI
#define PAD_CFG_GPI(pad, pull, rst)
Definition:
gpio_defs.h:284
PAD_CFG_GPI_SCI_LOW
#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig)
Definition:
gpio_defs.h:452
PAD_CFG_NF
#define PAD_CFG_NF(pad, pull, rst, func)
Definition:
gpio_defs.h:197
PAD_CFG_GPI_APIC
#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv)
Definition:
gpio_defs.h:376
PAD_CFG_GPO
#define PAD_CFG_GPO(pad, val, rst)
Definition:
gpio_defs.h:247
PAD_CFG_GPI_GPIO_DRIVER
#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst)
Definition:
gpio_defs.h:323
pad_config
Definition:
gpio.h:75
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gpio.c
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