coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c File Reference
#include <program_loading.h>
#include <console/console.h>
#include <cbmem.h>
#include <soc/ti/am335x/sdram.h>
#include "ddr3.h"
Include dependency graph for romstage.c:

Go to the source code of this file.

Functions

void main (void)
 

Variables

const struct ctrl_ioregs ioregs_bonelt
 
static const struct ddr_data ddr3_beagleblack_data
 
static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data
 
static struct emif_regs ddr3_beagleblack_emif_reg_data
 

Function Documentation

◆ main()

Variable Documentation

◆ ddr3_beagleblack_cmd_ctrl_data

const struct cmd_control ddr3_beagleblack_cmd_ctrl_data
static
Initial value:
= {
.cmd0csratio = MT41K256M16HA125E_RATIO,
.cmd1csratio = MT41K256M16HA125E_RATIO,
.cmd2csratio = MT41K256M16HA125E_RATIO,
}
#define MT41K256M16HA125E_INVERT_CLKOUT
Definition: ddr3.h:20
#define MT41K256M16HA125E_RATIO
Definition: ddr3.h:19

Definition at line 1 of file romstage.c.

Referenced by main().

◆ ddr3_beagleblack_data

const struct ddr_data ddr3_beagleblack_data
static
Initial value:
= {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
}
#define MT41K256M16HA125E_WR_DQS
Definition: ddr3.h:22
#define MT41K256M16HA125E_PHY_WR_DATA
Definition: ddr3.h:23
#define MT41K256M16HA125E_PHY_FIFO_WE
Definition: ddr3.h:24
#define MT41K256M16HA125E_RD_DQS
Definition: ddr3.h:21

Definition at line 1 of file romstage.c.

Referenced by main().

◆ ddr3_beagleblack_emif_reg_data

struct emif_regs ddr3_beagleblack_emif_reg_data
static
Initial value:
= {
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
}
#define MT41K256M16HA125E_EMIF_TIM3
Definition: ddr3.h:15
#define MT41K256M16HA125E_EMIF_TIM2
Definition: ddr3.h:14
#define MT41K256M16HA125E_EMIF_SDCFG
Definition: ddr3.h:16
#define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK
Definition: ddr3.h:27
#define MT41K256M16HA125E_EMIF_READ_LATENCY
Definition: ddr3.h:12
#define MT41K256M16HA125E_EMIF_TIM1
Definition: ddr3.h:13
#define MT41K256M16HA125E_ZQ_CFG
Definition: ddr3.h:18
#define MT41K256M16HA125E_EMIF_SDREF
Definition: ddr3.h:17

Definition at line 1 of file romstage.c.

Referenced by main().

◆ ioregs_bonelt

const struct ctrl_ioregs ioregs_bonelt
Initial value:
= {
}
#define MT41K256M16HA125E_IOCTRL_VALUE
Definition: ddr3.h:25

Definition at line 1 of file romstage.c.

Referenced by main().