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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <acpi/acpi_device.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <stdlib.h>
#include <southbridge/intel/common/acpi_pirq_gen.h>
#include <southbridge/intel/common/rcba_pirq.h>
#include <southbridge/intel/common/rcba.h>
Go to the source code of this file.
Macros | |
#define | MAX_SLOT 31 |
#define | MIN_SLOT 19 |
Functions | |
static enum pirq | map_pirq (const struct device *dev, const enum pci_pin pci_pin) |
void | intel_acpi_gen_def_acpi_pirq (const struct device *lpc) |
Variables | |
static const u32 | pirq_dir_route_reg [MAX_SLOT - MIN_SLOT+1] |
#define MAX_SLOT 31 |
Definition at line 12 of file rcba_pirq.c.
#define MIN_SLOT 19 |
Definition at line 13 of file rcba_pirq.c.
Definition at line 46 of file rcba_pirq.c.
References acpi_device_path(), slot_pin_irq_map::apic_gsi, BIOS_DEBUG, BIOS_ERR, BIOS_SPEW, calloc(), dev_path(), pci_path::devfn, free(), intel_write_pci0_PRT(), is_slot_pin_assigned(), map_pirq(), MAX_SLOTS, device::path, device_path::pci, pci_dev, PCI_INT_A, PCI_INT_D, PCI_INT_MAX, PCI_INTERRUPT_PIN, pci_read_config8(), PCI_SLOT, pcidev_on_root(), slot_pin_irq_map::pic_pirq, slot_pin_irq_map::pin, PIRQ_COUNT, pirq_idx(), PIRQ_INVALID, PIRQ_SOURCE_PATH, printk, device::sibling, slot_pin_irq_map::slot, snprintf(), pic_pirq_map::source_path, and pic_pirq_map::type.
Referenced by southbridge_fill_ssdt().
Definition at line 15 of file rcba_pirq.c.