coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 
6 /* Pad configuration in ramstage */
7 static const struct pad_config gpio_table[] = {
8  /* A10 : WWAN_EN */
9  PAD_CFG_GPO(GPP_A10, 1, PWROK),
10  /* A11 : TOUCH_RPT_EN ==> NC */
12 
13  /* B7 : PCIE_CLKREQ2_N ==> WWAN_SAR_DETECT_ODL*/
14  PAD_CFG_GPO(GPP_B7, 1, DEEP),
15  /* B8 : WLAN_CLKREQ_ODL ==> NC */
16  PAD_NC(GPP_B8, NONE),
17 
18  /* C18 : AP_I2C_EMR_SDA ==> NC */
20  /* C19 : AP_I2C_EMR_SCL ==> NC */
22 
23  /* D0 : WWAN_HOST_WAKE ==> WWAN_WDISABLE_L */
24  PAD_CFG_GPO(GPP_D0, 1, DEEP),
25  /* D1 : WLAN_PERST_L ==> NC */
26  PAD_NC(GPP_D1, NONE),
27  /* D3 : WLAN_PCIE_WAKE_ODL ==> NC */
28  PAD_NC(GPP_D3, NONE),
29  /* D4 : TOUCH_INT_ODL ==> NC */
30  PAD_NC(GPP_D4, NONE),
31  /* D5 : TOUCH_RESET_L ==> NC */
32  PAD_NC(GPP_D5, NONE),
33  /* D6 : EN_PP3300_TOUCH_S0 ==> NC */
34  PAD_NC(GPP_D6, NONE),
35  /* D12 : WCAM_RST_L ==> NC */
37  /* D14 : EN_PP1200_CAMERA ==> NC */
39  /* D15 : UCAM_RST_L ==> NC */
41  /* D19 : WWAN_WLAN_COEX1 ==> NC */
43  /* D20 : WWAN_WLAN_COEX2 ==> NC */
45  /* D21 : WWAN_WLAN_COEX3 ==> NC */
47 
48  /* E2 : CLK_24M_WCAM ==> NC */
49  PAD_NC(GPP_E2, NONE),
50 
51  /* H4 : AP_I2C_TS_SDA ==> NC */
52  PAD_NC(GPP_H4, NONE),
53  /* H5 : AP_I2C_TS_SCL ==> NC */
54  PAD_NC(GPP_H5, NONE),
55  /* H6 : AP_I2C_CAM_SDA ==> NC */
56  PAD_NC(GPP_H6, NONE),
57  /* H7 : AP_I2C_CAM_SCL ==> NC */
58  PAD_NC(GPP_H7, NONE),
59  /* H17 : WWAN_RST_L */
60  PAD_CFG_GPO(GPP_H17, 0, PLTRST),
61 
62  /* S2 : DMIC1_CLK ==> NC */
63  PAD_NC(GPP_S2, NONE),
64  /* S3 : DMIC1_DATA ==> NC */
65  PAD_NC(GPP_S3, NONE),
66 };
67 
68 const struct pad_config *variant_override_gpio_table(size_t *num)
69 {
70  *num = ARRAY_SIZE(gpio_table);
71  return gpio_table;
72 }
#define GPP_D1
#define GPP_D14
#define GPP_H17
#define GPP_D12
#define GPP_D6
#define GPP_H6
#define GPP_H7
#define GPP_D5
#define GPP_C18
#define GPP_S3
#define GPP_B8
Definition: gpio_soc_defs.h:61
#define GPP_D4
#define GPP_E2
#define GPP_H5
#define GPP_A10
#define GPP_D0
#define GPP_A11
#define GPP_C19
#define GPP_S2
#define GPP_D19
#define GPP_D15
#define GPP_H4
#define GPP_B7
Definition: gpio_soc_defs.h:60
#define GPP_D3
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define GPP_D21
#define GPP_D20
const struct pad_config *__weak variant_override_gpio_table(size_t *num)
Definition: gpio.c:450
static const struct pad_config gpio_table[]
Definition: gpio.c:7
#define PAD_NC(pin)
Definition: gpio_defs.h:263
#define PAD_CFG_GPO(pad, val, rst)
Definition: gpio_defs.h:247