9 #define ME_RETRY 100000
16 #define PCI_CPU_DEVICE PCI_DEV(0,0,0)
17 #define PCI_CPU_MEBASE_L 0x70
18 #define PCI_CPU_MEBASE_H 0x74
20 #define PCI_ME_HFS 0x40
21 #define ME_HFS_CWS_RESET 0
22 #define ME_HFS_CWS_INIT 1
23 #define ME_HFS_CWS_REC 2
24 #define ME_HFS_CWS_NORMAL 5
25 #define ME_HFS_CWS_WAIT 6
26 #define ME_HFS_CWS_TRANS 7
27 #define ME_HFS_CWS_INVALID 8
28 #define ME_HFS_STATE_PREBOOT 0
29 #define ME_HFS_STATE_M0_UMA 1
30 #define ME_HFS_STATE_M3 4
31 #define ME_HFS_STATE_M0 5
32 #define ME_HFS_STATE_BRINGUP 6
33 #define ME_HFS_STATE_ERROR 7
34 #define ME_HFS_ERROR_NONE 0
35 #define ME_HFS_ERROR_UNCAT 1
36 #define ME_HFS_ERROR_IMAGE 3
37 #define ME_HFS_ERROR_DEBUG 4
38 #define ME_HFS_MODE_NORMAL 0
39 #define ME_HFS_MODE_DEBUG 2
40 #define ME_HFS_MODE_DIS 3
41 #define ME_HFS_MODE_OVER_JMPR 4
42 #define ME_HFS_MODE_OVER_MEI 5
43 #define ME_HFS_BIOS_DRAM_ACK 1
44 #define ME_HFS_ACK_NO_DID 0
45 #define ME_HFS_ACK_RESET 1
46 #define ME_HFS_ACK_PWR_CYCLE 2
47 #define ME_HFS_ACK_S3 3
48 #define ME_HFS_ACK_S4 4
49 #define ME_HFS_ACK_S5 5
50 #define ME_HFS_ACK_GBL_RESET 6
51 #define ME_HFS_ACK_CONTINUE 7
72 #define PCI_ME_UMA 0x44
85 #define PCI_ME_H_GS 0x4c
86 #define ME_INIT_DONE 1
87 #define ME_INIT_STATUS_SUCCESS 0
88 #define ME_INIT_STATUS_NOMEM 1
89 #define ME_INIT_STATUS_ERROR 2
101 #define PCI_ME_GMES 0x48
102 #define ME_GMES_PHASE_ROM 0
103 #define ME_GMES_PHASE_BUP 1
104 #define ME_GMES_PHASE_UKERNEL 2
105 #define ME_GMES_PHASE_POLICY 3
106 #define ME_GMES_PHASE_MODULE 4
107 #define ME_GMES_PHASE_UNKNOWN 5
108 #define ME_GMES_PHASE_HOST 6
130 #define PCI_ME_HERES 0xbc
131 #define PCI_ME_EXT_SHA1 0x00
132 #define PCI_ME_EXT_SHA256 0x02
133 #define PCI_ME_HER(x) (0xc0+(4*(x)))
149 #define MEI_H_CB_WW 0x00
150 #define MEI_H_CSR 0x04
151 #define MEI_ME_CB_RW 0x08
152 #define MEI_ME_CSR_HA 0x0c
166 #define MEI_ADDRESS_CORE 0x01
167 #define MEI_ADDRESS_AMT 0x02
168 #define MEI_ADDRESS_RESERVED 0x03
169 #define MEI_ADDRESS_WDT 0x04
170 #define MEI_ADDRESS_MKHI 0x07
171 #define MEI_ADDRESS_ICC 0x08
172 #define MEI_ADDRESS_THERMAL 0x09
174 #define MEI_HOST_ADDRESS 0
184 #define MKHI_GROUP_ID_CBM 0x00
185 #define MKHI_GROUP_ID_FWCAPS 0x03
186 #define MKHI_GROUP_ID_MDES 0x08
187 #define MKHI_GROUP_ID_GEN 0xff
189 #define MKHI_GLOBAL_RESET 0x0b
191 #define MKHI_FWCAPS_GET_RULE 0x02
192 #define MKHI_FWCAPS_SET_RULE 0x03
194 #define MKHI_DISABLE_RULE_ID 0x06
196 #define CMOS_ME_STATE(state) ((state) & 0x1)
197 #define CMOS_ME_CHANGED(state) (((state) & 0x2) >> 1)
198 #define CMOS_ME_STATE_NORMAL 0
199 #define CMOS_ME_STATE_DISABLED 1
200 #define CMOS_ME_STATE_CHANGED 2
202 #define ME_ENABLE_TIMEOUT 20000
209 #define MKHI_MDES_ENABLE 0x09
211 #define MKHI_GET_FW_VERSION 0x02
212 #define MKHI_END_OF_POST 0x0c
213 #define MKHI_FEATURE_OVERRIDE 0x14
234 #define HECI_EOP_STATUS_SUCCESS 0x0
235 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
237 #define CBM_RR_GLOBAL_RESET 0x01
239 #define GLOBAL_RESET_BIOS_MRC 0x01
240 #define GLOBAL_RESET_BIOS_POST 0x02
241 #define GLOBAL_RESET_MEBX 0x03
263 #ifndef __SIMPLE_DEVICE__
279 void *req_data,
void *rsp_data,
int rsp_bytes);
298 u32 major_version : 16;
299 u32 minor_version : 16;
300 u32 hotfix_version : 16;
301 u32 build_version : 16;
306 u8 icc_profile_soft_strap;
307 u8 icc_profile_index;
309 u32 register_lock_mask[3];
315 u32 manageability : 1;
322 u32 icc_over_clocking : 1;
337 u16 authenticate_module : 1;
338 u16 s3authentication : 1;
339 u16 flash_wear_out : 1;
340 u16 flash_variable_security : 1;
348 u8 last_theft_trigger;
void intel_me_status(void)
@ ME_FIRMWARE_UPDATE_BIOS_PATH
bool is_mei_base_address_valid(void)
int intel_mei_setup(struct device *dev)
void update_mei_base_address(void)
void exit_soft_temp_disable(struct device *dev)
int intel_early_me_init(void)
void intel_early_me_status(void)
const char *const me_get_bios_path_string(int path)
void intel_me_finalize_smm(void)
int intel_me_extend_valid(struct device *dev)
void write_host_csr(struct mei_csr *csr)
void intel_me_hide(struct device *dev)
int intel_early_me_uma_size(void)
void mei_read_dword_ptr(void *ptr, int offset)
void read_host_csr(struct mei_csr *csr)
bool enter_soft_temp_disable(void)
void mei_write_dword_ptr(void *ptr, int offset)
int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, void *req_data, void *rsp_data, int rsp_bytes)
void exit_soft_temp_disable_wait(struct device *dev)
void enter_soft_temp_disable_wait(void)
int intel_early_me_init_done(u8 status)
void read_me_csr(struct mei_csr *csr)
u32 platform_target_market_type
u32 intel_me_fw_image_type
u32 platform_target_usage_type
mefwcaps_sku fw_capabilities
platform_type_rule_data rule_data
mbp_platform_key platform_key
mbp_rom_bist_data rom_bist_data
mbp_plat_type fw_plat_type
mbp_icc_profile icc_profile
mbp_fw_version_name fw_version_name
u16 recovery_build_number
u32 extend_feature_present