9 #define ME_RETRY 100000
16 #define PCI_CPU_DEVICE PCI_DEV(0,0,0)
17 #define PCI_CPU_MEBASE_L 0x70
18 #define PCI_CPU_MEBASE_H 0x74
20 #define PCI_ME_HFS 0x40
21 #define ME_HFS_CWS_RESET 0
22 #define ME_HFS_CWS_INIT 1
23 #define ME_HFS_CWS_REC 2
24 #define ME_HFS_CWS_NORMAL 5
25 #define ME_HFS_CWS_WAIT 6
26 #define ME_HFS_CWS_TRANS 7
27 #define ME_HFS_CWS_INVALID 8
28 #define ME_HFS_STATE_PREBOOT 0
29 #define ME_HFS_STATE_M0_UMA 1
30 #define ME_HFS_STATE_M3 4
31 #define ME_HFS_STATE_M0 5
32 #define ME_HFS_STATE_BRINGUP 6
33 #define ME_HFS_STATE_ERROR 7
34 #define ME_HFS_ERROR_NONE 0
35 #define ME_HFS_ERROR_UNCAT 1
36 #define ME_HFS_ERROR_IMAGE 3
37 #define ME_HFS_ERROR_DEBUG 4
38 #define ME_HFS_MODE_NORMAL 0
39 #define ME_HFS_MODE_DEBUG 2
40 #define ME_HFS_MODE_DIS 3
41 #define ME_HFS_MODE_OVER_JMPR 4
42 #define ME_HFS_MODE_OVER_MEI 5
43 #define ME_HFS_BIOS_DRAM_ACK 1
44 #define ME_HFS_ACK_NO_DID 0
45 #define ME_HFS_ACK_RESET 1
46 #define ME_HFS_ACK_PWR_CYCLE 2
47 #define ME_HFS_ACK_S3 3
48 #define ME_HFS_ACK_S4 4
49 #define ME_HFS_ACK_S5 5
50 #define ME_HFS_ACK_GBL_RESET 6
51 #define ME_HFS_ACK_CONTINUE 7
72 #define PCI_ME_UMA 0x44
85 #define PCI_ME_H_GS 0x4c
86 #define ME_INIT_DONE 1
87 #define ME_INIT_STATUS_SUCCESS 0
88 #define ME_INIT_STATUS_NOMEM 1
89 #define ME_INIT_STATUS_ERROR 2
90 #define ME_INIT_STATUS_SUCCESS_OTHER 3
107 #define PCI_ME_HFS2 0x48
109 #define ME_HFS2_PHASE_ROM 0
110 #define ME_HFS2_PHASE_BUP 1
111 #define ME_HFS2_PHASE_UKERNEL 2
112 #define ME_HFS2_PHASE_POLICY 3
113 #define ME_HFS2_PHASE_MODULE_LOAD 4
114 #define ME_HFS2_PHASE_UNKNOWN 5
115 #define ME_HFS2_PHASE_HOST_COMM 6
118 #define ME_HFS2_STATE_ROM_BEGIN 0
119 #define ME_HFS2_STATE_ROM_DISABLE 6
121 #define ME_HFS2_STATE_BUP_INIT 0
122 #define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1
123 #define ME_HFS2_STATE_BUP_FLOW_DET 4
124 #define ME_HFS2_STATE_BUP_VSCC_ERR 8
125 #define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa
126 #define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb
127 #define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd
128 #define ME_HFS2_STATE_BUP_M3 0x11
129 #define ME_HFS2_STATE_BUP_M0 0x12
130 #define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13
131 #define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15
132 #define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17
133 #define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18
134 #define ME_HFS2_STATE_BUP_T32_MISSING 0x1c
135 #define ME_HFS2_STATE_BUP_WAIT_DID 0x1f
136 #define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20
137 #define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21
138 #define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22
139 #define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23
140 #define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24
141 #define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25
142 #define ME_HFS2_STATE_BUP_M0_CLK 0x26
143 #define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27
144 #define ME_HFS2_STATE_BUP_TEMP_DIS 0x28
145 #define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32
147 #define ME_HFS2_STATE_POLICY_ENTRY 0
148 #define ME_HFS2_STATE_POLICY_RCVD_S3 3
149 #define ME_HFS2_STATE_POLICY_RCVD_S4 4
150 #define ME_HFS2_STATE_POLICY_RCVD_S5 5
151 #define ME_HFS2_STATE_POLICY_RCVD_UPD 6
152 #define ME_HFS2_STATE_POLICY_RCVD_PCR 7
153 #define ME_HFS2_STATE_POLICY_RCVD_NPCR 8
154 #define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9
155 #define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa
156 #define ME_HFS2_STATE_POLICY_RCVD_DID 0xb
157 #define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc
158 #define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd
159 #define ME_HFS2_STATE_POLICY_FPB_ERR 0xe
160 #define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf
161 #define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10
163 #define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0
164 #define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1
165 #define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2
166 #define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3
167 #define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4
168 #define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5
169 #define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6
170 #define ME_HFS2_PMEVENT_S0MO_SXM3 7
171 #define ME_HFS2_PMEVENT_SXM3_S0M0 8
172 #define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9
173 #define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa
174 #define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb
175 #define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc
197 #define PCI_ME_H_GS2 0x70
198 #define PCI_ME_MBP_GIVE_UP 0x01
200 #define PCI_ME_HERES 0xbc
201 #define PCI_ME_EXT_SHA1 0x00
202 #define PCI_ME_EXT_SHA256 0x02
203 #define PCI_ME_HER(x) (0xc0+(4*(x)))
219 #define MEI_H_CB_WW 0x00
220 #define MEI_H_CSR 0x04
221 #define MEI_ME_CB_RW 0x08
222 #define MEI_ME_CSR_HA 0x0c
239 #define MEI_ADDRESS_CORE 0x01
240 #define MEI_ADDRESS_AMT 0x02
241 #define MEI_ADDRESS_RESERVED 0x03
242 #define MEI_ADDRESS_WDT 0x04
243 #define MEI_ADDRESS_MKHI 0x07
244 #define MEI_ADDRESS_ICC 0x08
245 #define MEI_ADDRESS_THERMAL 0x09
247 #define MEI_HOST_ADDRESS 0
260 #define MKHI_GROUP_ID_CBM 0x00
261 #define MKHI_GROUP_ID_FWCAPS 0x03
262 #define MKHI_GROUP_ID_MDES 0x08
263 #define MKHI_GROUP_ID_GEN 0xff
265 #define MKHI_GLOBAL_RESET 0x0b
267 #define MKHI_FWCAPS_GET_RULE 0x02
269 #define MKHI_MDES_ENABLE 0x09
271 #define MKHI_GET_FW_VERSION 0x02
272 #define MKHI_END_OF_POST 0x0c
273 #define MKHI_FEATURE_OVERRIDE 0x14
295 #define ICC_SET_CLOCK_ENABLES 0x3
296 #define ICC_API_VERSION_LYNXPOINT 0x00030000
313 #define HECI_EOP_STATUS_SUCCESS 0x0
314 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
316 #define CBM_RR_GLOBAL_RESET 0x01
318 #define GLOBAL_RESET_BIOS_MRC 0x01
319 #define GLOBAL_RESET_BIOS_POST 0x02
320 #define GLOBAL_RESET_MEBX 0x03
351 #define MBP_APPID_KERNEL 1
352 #define MBP_APPID_INTEL_AT 3
353 #define MBP_APPID_HWA 4
354 #define MBP_APPID_ICC 5
355 #define MBP_APPID_NFC 6
357 #define MBP_KERNEL_FW_VER_ITEM 1
358 #define MBP_KERNEL_FW_CAP_ITEM 2
359 #define MBP_KERNEL_ROM_BIST_ITEM 3
360 #define MBP_KERNEL_PLAT_KEY_ITEM 4
361 #define MBP_KERNEL_FW_TYPE_ITEM 5
362 #define MBP_KERNEL_MFS_FAILURE_ITEM 6
363 #define MBP_KERNEL_PLAT_TIME_ITEM 7
365 #define MBP_INTEL_AT_STATE_ITEM 1
367 #define MBP_ICC_PROFILE_ITEM 1
369 #define MBP_HWA_REQUEST_ITEM 1
371 #define MBP_NFC_SUPPORT_DATA_ITEM 1
373 #define MBP_MAKE_IDENT(appid, item) ((appid << 8) | item)
374 #define MBP_IDENT(appid, item) \
375 MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM)
void intel_me_status(void)
@ ME_FIRMWARE_UPDATE_BIOS_PATH
int intel_early_me_init(void)
void intel_early_me_status(void)
int intel_early_me_uma_size(void)
int intel_early_me_init_done(u8 status)
void intel_me_finalize(struct device *dev)
struct tdt_state_flag flags
u8 icc_profile_soft_strap
u32 pltrst_cpurst_time_ms
u32 wake_event_mrst_time_ms
mbp_me_firmware_type rule_data
struct mbp_rom_bist_data * rom_bist_data
struct mbp_at_state * at_state
struct mbp_nfc_data * nfc_data
struct mbp_plat_time * plat_time
struct mbp_platform_key * platform_key
struct mbp_plat_type * fw_plat_type
struct mbp_mefwcaps * fw_capabilities
struct mbp_icc_profile * icc_profile
struct mbp_fw_version_name * fw_version_name
u16 recovery_build_number
u32 extend_feature_present
u16 flash_variable_security