81 reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8);
void outw(u16 val, u16 port)
DEVTREE_CONST struct device * pcidev_on_root(uint8_t dev, uint8_t fn)
#define D31F0_SERIRQ_CNTL
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
static __always_inline void pci_or_config8(const struct device *dev, u16 reg, u8 ormask)
static __always_inline u8 pci_read_config8(const struct device *dev, u16 reg)
static __always_inline void pci_write_config16(const struct device *dev, u16 reg, u16 val)
static __always_inline void pci_write_config8(const struct device *dev, u16 reg, u8 val)
#define PCI_DEV(SEGBUS, DEV, FN)
static void enable_smbus(void)
void i82801ix_early_init(void)
void i82801ix_lpc_setup(void)
DEVTREE_CONST void * chip_info