coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_init.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
device/pci_ops.h
>
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#include <
southbridge/intel/i82801ix/i82801ix.h
>
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#include "
gm45.h
"
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void
gm45_early_init
(
void
)
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{
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const
pci_devfn_t
d0f0 =
PCI_DEV
(0, 0, 0);
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/* Setup MCHBAR. */
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pci_write_config32
(d0f0,
D0F0_MCHBAR_LO
, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1);
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/* Setup DMIBAR. */
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pci_write_config32
(d0f0,
D0F0_DMIBAR_LO
, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
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/* Setup EPBAR. */
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pci_write_config32
(d0f0,
D0F0_EPBAR_LO
, CONFIG_FIXED_EPBAR_MMIO_BASE | 1);
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pci_write_config32
(d0f0,
D0F0_PMBASE
,
DEFAULT_PMBASE
| 1);
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/* Set C0000-FFFFF to access RAM on both reads and writes */
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pci_write_config8
(d0f0,
D0F0_PAM
(0), 0x30);
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pci_write_config8
(d0f0,
D0F0_PAM
(1), 0x33);
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pci_write_config8
(d0f0,
D0F0_PAM
(2), 0x33);
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pci_write_config8
(d0f0,
D0F0_PAM
(3), 0x33);
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pci_write_config8
(d0f0,
D0F0_PAM
(4), 0x33);
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pci_write_config8
(d0f0,
D0F0_PAM
(5), 0x33);
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pci_write_config8
(d0f0,
D0F0_PAM
(6), 0x33);
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}
D0F0_PAM
#define D0F0_PAM(x)
Definition:
mainboard.c:13
gm45.h
D0F0_EPBAR_LO
#define D0F0_EPBAR_LO
Definition:
gm45.h:172
D0F0_MCHBAR_LO
#define D0F0_MCHBAR_LO
Definition:
gm45.h:174
D0F0_PMBASE
#define D0F0_PMBASE
Definition:
gm45.h:182
D0F0_DMIBAR_LO
#define D0F0_DMIBAR_LO
Definition:
gm45.h:180
i82801ix.h
pci_ops.h
pci_write_config32
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
Definition:
pci_ops.h:76
pci_write_config8
static __always_inline void pci_write_config8(const struct device *dev, u16 reg, u8 val)
Definition:
pci_ops.h:64
DEFAULT_PMBASE
#define DEFAULT_PMBASE
Definition:
iomap.h:14
gm45_early_init
void gm45_early_init(void)
Definition:
early_init.c:7
PCI_DEV
#define PCI_DEV(SEGBUS, DEV, FN)
Definition:
pci_type.h:14
pci_devfn_t
u32 pci_devfn_t
Definition:
pci_type.h:8
src
northbridge
intel
gm45
early_init.c
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