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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Macros | |
#define | DEBUG_PERIODIC_SMIS 0 |
#define | MAINBOARD_POWER_OFF 0 |
#define | MAINBOARD_POWER_ON 1 |
#define | MAINBOARD_POWER_KEEP 2 |
#define | IDE_TIM_PRI 0x40 /* IDE timings, primary */ |
#define | IDE_TIM_SEC 0x42 /* IDE timings, secondary */ |
#define | IDE_DECODE_ENABLE (1 << 15) |
#define | PCI_DMA_CFG 0x90 |
#define | SERIRQ_CNTL 0x64 |
#define | GEN_CNTL 0xd0 |
#define | GEN_STS 0xd4 |
#define | RTC_CONF 0xd8 |
#define | GEN_PMCON_3 0xa4 |
#define | PCICMD 0x04 |
#define | PMBASE 0x40 |
#define | PMBASE_ADDR 0x0400 |
#define | DEFAULT_PMBASE PMBASE_ADDR |
#define | ACPI_CNTL 0x44 |
#define | ACPI_EN (1 << 4) |
#define | BIOS_CNTL 0x4E |
#define | GPIO_BASE 0x58 |
#define | GPIO_CNTL 0x5C |
#define | GPIOBASE_ADDR 0x0500 |
#define | PIRQA_ROUT 0x60 |
#define | PIRQB_ROUT 0x61 |
#define | PIRQC_ROUT 0x62 |
#define | PIRQD_ROUT 0x63 |
#define | PIRQE_ROUT 0x68 |
#define | PIRQF_ROUT 0x69 |
#define | PIRQG_ROUT 0x6A |
#define | PIRQH_ROUT 0x6B |
#define | COM_DEC 0xE0 |
#define | LPC_EN 0xE6 |
#define | FUNC_DIS 0xF2 |
#define | CMD 0x04 |
#define | SBUS_NUM 0x19 |
#define | SUB_BUS_NUM 0x1A |
#define | SMLT 0x1B |
#define | IOBASE 0x1C |
#define | IOLIM 0x1D |
#define | MEMBASE 0x20 |
#define | MEMLIM 0x22 |
#define | CNF 0x50 |
#define | MTT 0x70 |
#define | PCI_MAST_STS 0x82 |
#define | RTC_FAILED (1 <<2) |
#define | PM1_STS 0x00 |
#define | WAK_STS (1 << 15) |
#define | PCIEXPWAK_STS (1 << 14) |
#define | PRBTNOR_STS (1 << 11) |
#define | RTC_STS (1 << 10) |
#define | PWRBTN_STS (1 << 8) |
#define | GBL_STS (1 << 5) |
#define | BM_STS (1 << 4) |
#define | TMROF_STS (1 << 0) |
#define | PM1_EN 0x02 |
#define | PCIEXPWAK_DIS (1 << 14) |
#define | RTC_EN (1 << 10) |
#define | PWRBTN_EN (1 << 8) |
#define | GBL_EN (1 << 5) |
#define | TMROF_EN (1 << 0) |
#define | PM1_CNT 0x04 |
#define | GBL_RLS (1 << 2) |
#define | BM_RLD (1 << 1) |
#define | SCI_EN (1 << 0) |
#define | PM1_TMR 0x08 |
#define | PROC_CNT 0x10 |
#define | LV2 0x14 |
#define | LV3 0x15 |
#define | LV4 0x16 |
#define | PM2_CNT 0x20 |
#define | GPE0_STS 0x28 |
#define | PME_B0_STS (1 << 13) |
#define | USB3_STS (1 << 12) |
#define | PME_STS (1 << 11) |
#define | BATLOW_STS (1 << 10) |
#define | GST_STS (1 << 9) |
#define | RI_STS (1 << 8) |
#define | SMB_WAK_STS (1 << 7) |
#define | TCOSCI_STS (1 << 6) |
#define | AC97_STS (1 << 5) |
#define | USB2_STS (1 << 4) |
#define | USB1_STS (1 << 3) |
#define | SWGPE_STS (1 << 2) |
#define | HOT_PLUG_STS (1 << 1) |
#define | THRM_STS (1 << 0) |
#define | GPE0_EN 0x2c |
#define | PME_B0_EN (1 << 13) |
#define | PME_EN (1 << 11) |
#define | SMI_EN 0x30 |
#define | EL_SMI_EN (1 << 25) |
#define | INTEL_USB2_EN (1 << 18) |
#define | LEGACY_USB2_EN (1 << 17) |
#define | PERIODIC_EN (1 << 14) |
#define | TCO_EN (1 << 13) |
#define | MCSMI_EN (1 << 11) |
#define | BIOS_RLS (1 << 7) |
#define | SWSMI_TMR_EN (1 << 6) |
#define | APMC_EN (1 << 5) |
#define | SLP_SMI_EN (1 << 4) |
#define | LEGACY_USB_EN (1 << 3) |
#define | BIOS_EN (1 << 2) |
#define | EOS (1 << 1) |
#define | GBL_SMI_EN (1 << 0) |
#define | SMI_STS 0x34 |
#define | ALT_GP_SMI_EN 0x38 |
#define | ALT_GP_SMI_STS 0x3a |
#define | GPE_CNTL 0x42 |
#define | DEVACT_STS 0x44 |
#define | SS_CNT 0x50 |
#define | C3_RES 0x54 |
#define | TCOBASE 0x60 /* TCO Base Address Register */ |
#define | TCO1_CNT 0x08 /* TCO1 Control Register */ |
#define | GEN_PMCON_1 0xa0 |
#define | GEN_PMCON_2 0xa2 |
#define | GEN_PMCON_3 0xa4 |
#define | RTC_BATTERY_DEAD (1 << 2) |
#define | RTC_POWER_FAILED (1 << 1) |
#define | SLEEP_AFTER_POWER_FAIL (1 << 0) |
Functions | |
void | i82801dx_enable (struct device *dev) |
void | i82801dx_early_init (void) |
void | aseg_smm_lock (void) |
#define AC97_STS (1 << 5) |
Definition at line 128 of file i82801dx.h.
#define ACPI_CNTL 0x44 |
Definition at line 60 of file i82801dx.h.
#define ACPI_EN (1 << 4) |
Definition at line 61 of file i82801dx.h.
#define ALT_GP_SMI_EN 0x38 |
Definition at line 153 of file i82801dx.h.
#define ALT_GP_SMI_STS 0x3a |
Definition at line 154 of file i82801dx.h.
#define APMC_EN (1 << 5) |
Definition at line 146 of file i82801dx.h.
#define BATLOW_STS (1 << 10) |
Definition at line 123 of file i82801dx.h.
#define BIOS_CNTL 0x4E |
Definition at line 62 of file i82801dx.h.
#define BIOS_EN (1 << 2) |
Definition at line 149 of file i82801dx.h.
#define BIOS_RLS (1 << 7) |
Definition at line 144 of file i82801dx.h.
#define BM_RLD (1 << 1) |
Definition at line 111 of file i82801dx.h.
#define BM_STS (1 << 4) |
Definition at line 101 of file i82801dx.h.
#define C3_RES 0x54 |
Definition at line 158 of file i82801dx.h.
#define CMD 0x04 |
Definition at line 80 of file i82801dx.h.
#define CNF 0x50 |
Definition at line 88 of file i82801dx.h.
#define COM_DEC 0xE0 |
Definition at line 74 of file i82801dx.h.
#define DEBUG_PERIODIC_SMIS 0 |
Definition at line 26 of file i82801dx.h.
#define DEFAULT_PMBASE PMBASE_ADDR |
Definition at line 59 of file i82801dx.h.
#define DEVACT_STS 0x44 |
Definition at line 156 of file i82801dx.h.
#define EL_SMI_EN (1 << 25) |
Definition at line 138 of file i82801dx.h.
#define EOS (1 << 1) |
Definition at line 150 of file i82801dx.h.
#define FUNC_DIS 0xF2 |
Definition at line 76 of file i82801dx.h.
#define GBL_EN (1 << 5) |
Definition at line 107 of file i82801dx.h.
#define GBL_RLS (1 << 2) |
Definition at line 110 of file i82801dx.h.
#define GBL_SMI_EN (1 << 0) |
Definition at line 151 of file i82801dx.h.
#define GBL_STS (1 << 5) |
Definition at line 100 of file i82801dx.h.
#define GEN_CNTL 0xd0 |
Definition at line 51 of file i82801dx.h.
#define GEN_PMCON_1 0xa0 |
Definition at line 163 of file i82801dx.h.
#define GEN_PMCON_2 0xa2 |
Definition at line 164 of file i82801dx.h.
#define GEN_PMCON_3 0xa4 |
Definition at line 165 of file i82801dx.h.
#define GEN_PMCON_3 0xa4 |
Definition at line 165 of file i82801dx.h.
#define GEN_STS 0xd4 |
Definition at line 52 of file i82801dx.h.
#define GPE0_EN 0x2c |
Definition at line 134 of file i82801dx.h.
#define GPE0_STS 0x28 |
Definition at line 119 of file i82801dx.h.
#define GPE_CNTL 0x42 |
Definition at line 155 of file i82801dx.h.
#define GPIO_BASE 0x58 |
Definition at line 63 of file i82801dx.h.
#define GPIO_CNTL 0x5C |
Definition at line 64 of file i82801dx.h.
#define GPIOBASE_ADDR 0x0500 |
Definition at line 65 of file i82801dx.h.
#define GST_STS (1 << 9) |
Definition at line 124 of file i82801dx.h.
#define HOT_PLUG_STS (1 << 1) |
Definition at line 132 of file i82801dx.h.
#define IDE_DECODE_ENABLE (1 << 15) |
Definition at line 47 of file i82801dx.h.
#define IDE_TIM_PRI 0x40 /* IDE timings, primary */ |
Definition at line 43 of file i82801dx.h.
#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ |
Definition at line 44 of file i82801dx.h.
#define INTEL_USB2_EN (1 << 18) |
Definition at line 139 of file i82801dx.h.
#define IOBASE 0x1C |
Definition at line 84 of file i82801dx.h.
#define IOLIM 0x1D |
Definition at line 85 of file i82801dx.h.
#define LEGACY_USB2_EN (1 << 17) |
Definition at line 140 of file i82801dx.h.
#define LEGACY_USB_EN (1 << 3) |
Definition at line 148 of file i82801dx.h.
#define LPC_EN 0xE6 |
Definition at line 75 of file i82801dx.h.
#define LV2 0x14 |
Definition at line 115 of file i82801dx.h.
#define LV3 0x15 |
Definition at line 116 of file i82801dx.h.
#define LV4 0x16 |
Definition at line 117 of file i82801dx.h.
#define MAINBOARD_POWER_KEEP 2 |
Definition at line 30 of file i82801dx.h.
#define MAINBOARD_POWER_OFF 0 |
Definition at line 28 of file i82801dx.h.
#define MAINBOARD_POWER_ON 1 |
Definition at line 29 of file i82801dx.h.
#define MCSMI_EN (1 << 11) |
Definition at line 143 of file i82801dx.h.
#define MEMBASE 0x20 |
Definition at line 86 of file i82801dx.h.
#define MEMLIM 0x22 |
Definition at line 87 of file i82801dx.h.
#define MTT 0x70 |
Definition at line 89 of file i82801dx.h.
#define PCI_DMA_CFG 0x90 |
Definition at line 49 of file i82801dx.h.
#define PCI_MAST_STS 0x82 |
Definition at line 90 of file i82801dx.h.
#define PCICMD 0x04 |
Definition at line 56 of file i82801dx.h.
#define PCIEXPWAK_DIS (1 << 14) |
Definition at line 104 of file i82801dx.h.
#define PCIEXPWAK_STS (1 << 14) |
Definition at line 96 of file i82801dx.h.
#define PERIODIC_EN (1 << 14) |
Definition at line 141 of file i82801dx.h.
#define PIRQA_ROUT 0x60 |
Definition at line 66 of file i82801dx.h.
#define PIRQB_ROUT 0x61 |
Definition at line 67 of file i82801dx.h.
#define PIRQC_ROUT 0x62 |
Definition at line 68 of file i82801dx.h.
#define PIRQD_ROUT 0x63 |
Definition at line 69 of file i82801dx.h.
#define PIRQE_ROUT 0x68 |
Definition at line 70 of file i82801dx.h.
#define PIRQF_ROUT 0x69 |
Definition at line 71 of file i82801dx.h.
#define PIRQG_ROUT 0x6A |
Definition at line 72 of file i82801dx.h.
#define PIRQH_ROUT 0x6B |
Definition at line 73 of file i82801dx.h.
#define PM1_CNT 0x04 |
Definition at line 109 of file i82801dx.h.
#define PM1_EN 0x02 |
Definition at line 103 of file i82801dx.h.
#define PM1_STS 0x00 |
Definition at line 94 of file i82801dx.h.
#define PM1_TMR 0x08 |
Definition at line 113 of file i82801dx.h.
#define PM2_CNT 0x20 |
Definition at line 118 of file i82801dx.h.
#define PMBASE 0x40 |
Definition at line 57 of file i82801dx.h.
#define PMBASE_ADDR 0x0400 |
Definition at line 58 of file i82801dx.h.
#define PME_B0_EN (1 << 13) |
Definition at line 135 of file i82801dx.h.
#define PME_B0_STS (1 << 13) |
Definition at line 120 of file i82801dx.h.
#define PME_EN (1 << 11) |
Definition at line 136 of file i82801dx.h.
#define PME_STS (1 << 11) |
Definition at line 122 of file i82801dx.h.
#define PRBTNOR_STS (1 << 11) |
Definition at line 97 of file i82801dx.h.
#define PROC_CNT 0x10 |
Definition at line 114 of file i82801dx.h.
#define PWRBTN_EN (1 << 8) |
Definition at line 106 of file i82801dx.h.
#define PWRBTN_STS (1 << 8) |
Definition at line 99 of file i82801dx.h.
#define RI_STS (1 << 8) |
Definition at line 125 of file i82801dx.h.
#define RTC_BATTERY_DEAD (1 << 2) |
Definition at line 168 of file i82801dx.h.
#define RTC_CONF 0xd8 |
Definition at line 53 of file i82801dx.h.
#define RTC_EN (1 << 10) |
Definition at line 105 of file i82801dx.h.
#define RTC_FAILED (1 <<2) |
Definition at line 92 of file i82801dx.h.
#define RTC_POWER_FAILED (1 << 1) |
Definition at line 169 of file i82801dx.h.
#define RTC_STS (1 << 10) |
Definition at line 98 of file i82801dx.h.
#define SBUS_NUM 0x19 |
Definition at line 81 of file i82801dx.h.
#define SCI_EN (1 << 0) |
Definition at line 112 of file i82801dx.h.
#define SERIRQ_CNTL 0x64 |
Definition at line 50 of file i82801dx.h.
#define SLEEP_AFTER_POWER_FAIL (1 << 0) |
Definition at line 170 of file i82801dx.h.
#define SLP_SMI_EN (1 << 4) |
Definition at line 147 of file i82801dx.h.
#define SMB_WAK_STS (1 << 7) |
Definition at line 126 of file i82801dx.h.
#define SMI_EN 0x30 |
Definition at line 137 of file i82801dx.h.
#define SMI_STS 0x34 |
Definition at line 152 of file i82801dx.h.
#define SMLT 0x1B |
Definition at line 83 of file i82801dx.h.
#define SS_CNT 0x50 |
Definition at line 157 of file i82801dx.h.
#define SUB_BUS_NUM 0x1A |
Definition at line 82 of file i82801dx.h.
#define SWGPE_STS (1 << 2) |
Definition at line 131 of file i82801dx.h.
#define SWSMI_TMR_EN (1 << 6) |
Definition at line 145 of file i82801dx.h.
#define TCO1_CNT 0x08 /* TCO1 Control Register */ |
Definition at line 161 of file i82801dx.h.
#define TCO_EN (1 << 13) |
Definition at line 142 of file i82801dx.h.
#define TCOBASE 0x60 /* TCO Base Address Register */ |
Definition at line 160 of file i82801dx.h.
#define TCOSCI_STS (1 << 6) |
Definition at line 127 of file i82801dx.h.
#define THRM_STS (1 << 0) |
Definition at line 133 of file i82801dx.h.
#define TMROF_EN (1 << 0) |
Definition at line 108 of file i82801dx.h.
#define TMROF_STS (1 << 0) |
Definition at line 102 of file i82801dx.h.
#define USB1_STS (1 << 3) |
Definition at line 130 of file i82801dx.h.
#define USB2_STS (1 << 4) |
Definition at line 129 of file i82801dx.h.
#define USB3_STS (1 << 12) |
Definition at line 121 of file i82801dx.h.
#define WAK_STS (1 << 15) |
Definition at line 95 of file i82801dx.h.
Definition at line 315 of file smi.c.
References BIOS_DEBUG, C_BASE_SEG, D_LCK, G_SMRAME, northbridge_write_smram(), and printk.
Referenced by lpc_init().
Definition at line 6 of file early_smbus.c.
References enable_smbus().
Referenced by mainboard_romstage_entry().
Definition at line 8 of file i82801dx.c.
References pci_path::devfn, device::enabled, FUNC_DIS, device::path, device_path::pci, PCI_DEVFN, PCI_FUNC, pci_read_config16(), PCI_SLOT, pci_write_config16(), and pcidev_path_on_root().