coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
i82801dx.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/device.h>
4 #include <device/pci.h>
5 #include <device/pci_ops.h>
6 #include "i82801dx.h"
7 
8 void i82801dx_enable(struct device *dev)
9 {
10  unsigned int index = 0;
11  uint8_t bHasDisableBit = 0;
12  uint16_t cur_disable_mask, new_disable_mask;
13 
14 // all 82801dbm devices are in bus 0
15  unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc
16  struct device *lpc_dev = pcidev_path_on_root(devfn); // 0
17  if (!lpc_dev)
18  return;
19 
20  // Calculate disable bit position for specified device:function
21  // NOTE: For ICH-4, only the following devices can be disabled:
22  // D31: F0, F1, F3, F5, F6,
23  // D29: F0, F1, F2, F7
24 
25  if (PCI_SLOT(dev->path.pci.devfn) == 31) {
26  index = PCI_FUNC(dev->path.pci.devfn);
27 
28  switch (index) {
29  case 0:
30  case 1:
31  case 3:
32  case 5:
33  case 6:
34  bHasDisableBit = 1;
35  break;
36 
37  default:
38  break;
39  };
40 
41  if (index == 0)
42  index = 14; // D31:F0 bit is an exception
43 
44  } else if (PCI_SLOT(dev->path.pci.devfn) == 29) {
45  index = 8 + PCI_FUNC(dev->path.pci.devfn);
46 
47  if ((PCI_FUNC(dev->path.pci.devfn) < 3)
48  || (PCI_FUNC(dev->path.pci.devfn) == 7))
49  bHasDisableBit = 1;
50  }
51 
52  if (bHasDisableBit) {
53  cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
54  new_disable_mask = cur_disable_mask & ~(1 << index); // enable it
55  if (!dev->enabled) {
56  new_disable_mask |= (1 << index); // disable it
57  }
58  if (new_disable_mask != cur_disable_mask) {
59  pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
60  }
61  }
62 }
63 
65  CHIP_NAME("Intel ICH4/ICH4-M (82801Dx) Series Southbridge")
66  .enable_dev = i82801dx_enable,
67 };
#define FUNC_DIS
Definition: pm.h:62
DEVTREE_CONST struct device * pcidev_path_on_root(pci_devfn_t devfn)
Definition: device_const.c:255
struct chip_operations southbridge_intel_i82801dx_ops
Definition: i82801dx.c:64
void i82801dx_enable(struct device *dev)
Definition: i82801dx.c:8
#define CHIP_NAME(X)
Definition: device.h:32
static __always_inline u16 pci_read_config16(const struct device *dev, u16 reg)
Definition: pci_ops.h:52
static __always_inline void pci_write_config16(const struct device *dev, u16 reg, u16 val)
Definition: pci_ops.h:70
#define PCI_DEVFN(slot, func)
Definition: pci_def.h:548
#define PCI_FUNC(devfn)
Definition: pci_def.h:550
#define PCI_SLOT(devfn)
Definition: pci_def.h:549
unsigned short uint16_t
Definition: stdint.h:11
unsigned char uint8_t
Definition: stdint.h:8
struct pci_path pci
Definition: path.h:116
Definition: device.h:107
struct device_path path
Definition: device.h:115
unsigned int enabled
Definition: device.h:122
unsigned int devfn
Definition: path.h:54