coreboot
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gpio.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <soc/gpe.h>
4 #include <soc/gpio.h>
5 #include <variant/gpio.h>
6 
7 static const struct pad_config gpio_table[] = {
8  /* ------- GPIO Group GPD ------- */
9  PAD_CFG_GPI(GPD0, NONE, PWROK), // PM_BATLOW#
10  PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
11  PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP#
12  PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
13  PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#
14  PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#
15  PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A# (test point)
16  PAD_CFG_GPI(GPD7, NONE, PWROK), /* GPD_7 (crystal input,
17  low = signal ended,
18  high = differential)
19  */
20  PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK_R
21  PAD_NC(GPD9, NONE), // PCH_SLP_WLAN# (test point)
22  PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // NC
23  PAD_NC(GPD11, NONE), // LAN_DISABLE_N (test point)
24 
25  /* ------- GPIO Group GPP_A ------- */
26  PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
27  PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
28  PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
29  PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
30  PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
31  PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
32  PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
33  _PAD_CFG_STRUCT(GPP_A7, 0x80100100, 0x0000), // INTP_OUT
34  PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
35  PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // CLK_PCI_KBC_R
37  PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // LAN_WUP#
38  PAD_NC(GPP_A12, NONE), // ISH_GP_6_R (test point)
39  PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
40  PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // S4_STATE#
41  PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK#_R
44  PAD_CFG_GPO(GPP_A18, 1, DEEP), // SB_BLON
47  PAD_NC(GPP_A21, NONE), // 3G_CONFIG2 (test point)
48  PAD_CFG_GPO(GPP_A22, 1, DEEP), // SATA_PWR_EN
49  PAD_NC(GPP_A23, NONE), // DGPU_PWM_SELECT# (test point)
50 
51  /* ------- GPIO Group GPP_B ------- */
52  PAD_CFG_GPI(GPP_B0, NONE, DEEP),// TPM_PIRQ#
53  PAD_NC(GPP_B1, NONE), // GPP_B1 (test point)
54  PAD_NC(GPP_B2, NONE), // VRALERTB# (test point)
55  PAD_CFG_GPI(GPP_B3, NONE, DEEP), // BT_EN_PCH
56  PAD_CFG_GPI(GPP_B4, UP_20K, DEEP), // EXTTS_SNI_DRV1
57  PAD_NC(GPP_B5, NONE),
58  PAD_NC(GPP_B6, NONE),
59  PAD_NC(GPP_B7, NONE),
60  PAD_NC(GPP_B8, NONE),
61  PAD_NC(GPP_B9, NONE),
62  PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // LAN_CLKREQ#
64  PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
65  PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
66  PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // SPKR_SMC_EXTSMI (PCH_SPKR)
70  PAD_CFG_GPI(GPP_B18, NONE, DEEP), // LPSS_GSPI0_MOSI (no reboot)
74  PAD_CFG_GPI(GPP_B22, NONE, DEEP), // LPSS_GSPI1_MOSI (boot strap)
75  PAD_CFG_GPI(GPP_B23, NONE, DEEP), // PCH_HOT_GNSS_DISABLE
76 
77  /* ------- GPIO Group GPP_C ------- */
78  PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
79  PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
80  PAD_CFG_GPI(GPP_C2, NONE, DEEP), // SKIN_THRM_SNSR_ALERT_N
81  PAD_CFG_GPI(GPP_C3, NONE, DEEP), // SML0_CLK
82  PAD_CFG_GPI(GPP_C4, NONE, DEEP), // SMK0_DATA
83  PAD_NC(GPP_C5, NONE), // GPP_C5 (test point)
84  PAD_CFG_GPI(GPP_C6, NONE, DEEP), // SMC_CPU_THERM
85  PAD_CFG_GPI(GPP_C7, NONE, DEEP), // SMD_CPU_THERM
86  PAD_NC(GPP_C8, NONE),
87  PAD_NC(GPP_C9, NONE),
94  PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP
95  PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP
96  PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // SMD_7411_I2C
97  PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // SMC_7411_I2C
98  //PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
99  //PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
100  PAD_NC(GPP_C22, NONE),
101  PAD_NC(GPP_C23, NONE),
102 
103  /* ------- GPIO Group GPP_D ------- */
104  PAD_NC(GPP_D0, NONE),
105  PAD_NC(GPP_D1, NONE),
106  PAD_NC(GPP_D2, NONE),
107  PAD_NC(GPP_D3, NONE),
108  PAD_CFG_GPI(GPP_D4, NONE, DEEP), // I2C2_SDA
109  PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RF_RST#
110  PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // XTAL_CLKREQ
111  PAD_NC(GPP_D7, NONE),
112  PAD_NC(GPP_D8, NONE),
113  PAD_NC(GPP_D9, NONE),
114  PAD_NC(GPP_D10, NONE),
115  PAD_NC(GPP_D11, NONE),
116  PAD_NC(GPP_D12, NONE),
117  PAD_NC(GPP_D13, NONE),
118  PAD_NC(GPP_D14, NONE),
119  PAD_NC(GPP_D15, NONE),
120  PAD_NC(GPP_D16, NONE),
121  PAD_NC(GPP_D17, NONE), // 100k pull down
122  PAD_NC(GPP_D18, NONE),
123  PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // MIC_CLK_PCH_R
124  PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // MIC_DATA_PCH_R
125  PAD_NC(GPP_D21, NONE),
126  PAD_NC(GPP_D22, NONE),
127  PAD_CFG_GPI(GPP_D23, NONE, DEEP), // I2C2_SCL
128 
129  /* ------- GPIO Group GPP_E ------- */
130  PAD_NC(GPP_E0, UP_20K), // SATAGP0 (test point)
131  PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1
132  PAD_CFG_GPI(GPP_E2, NONE, DEEP), // SATAGP2
133  PAD_CFG_GPI(GPP_E3, NONE, DEEP), // EXTTS_SNI_DRV0
134  PAD_CFG_GPI(GPP_E4, NONE, DEEP), // DEVSLP0
135  PAD_CFG_GPI(GPP_E5, NONE, DEEP), // DEVSLP1
136  PAD_NC(GPP_E6, NONE), // PCH_MUTE# (test point)
137  PAD_CFG_GPI_APIC_LOW(GPP_E7, NONE, PLTRST), // TP_ATTN#
138  PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
139  PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0#
140  PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1#
141  PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2#
142  PAD_CFG_GPI(GPP_E12, NONE, DEEP), // VISACH2_D3
143 
144  /* ------- GPIO Group GPP_F ------- */
145  PAD_CFG_GPI(GPP_F0, NONE, DEEP), // SATAGP3
146  PAD_NC(GPP_F1, NONE),
147  PAD_NC(GPP_F2, NONE), // ODD_DA#_R (test point)
148  PAD_NC(GPP_F3, NONE), // (test point)
149  PAD_NC(GPP_F4, NONE),
150  PAD_CFG_GPI(GPP_F5, NONE, DEEP), // KBLED_DET
151  PAD_CFG_GPI(GPP_F6, NONE, DEEP), // DEVSLP4
152  PAD_CFG_GPI(GPP_F7, NONE, DEEP), // LIGHT_KB_DET#
153  PAD_CFG_GPI(GPP_F8, NONE, DEEP), // GPP_F8
154  PAD_CFG_GPI(GPP_F9, NONE, DEEP), // GPP_F9
155  PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS_REC
156  PAD_CFG_GPI(GPP_F11, NONE, DEEP), // PCH_RSVD
157  PAD_CFG_GPI(GPP_F12, NONE, DEEP), // MFG_MODE
158  PAD_CFG_GPI(GPP_F13, NONE, DEEP), // GP39_GFX_CRB_DETECT
159  PAD_CFG_GPI(GPP_F14, NONE, DEEP), // 10k pull up to H_SKTOCC_N
160  PAD_CFG_GPI(GPP_F15, NONE, DEEP), // USB_OC4#
161  PAD_CFG_GPI(GPP_F16, NONE, DEEP), // USB_OC5#
162  PAD_CFG_GPI(GPP_F17, NONE, DEEP), // USB_OC6#
163  PAD_CFG_GPI(GPP_F18, NONE, DEEP), // USB_OC7#
164  //PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
165  PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
166  PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
167  //PAD_CFG_GPO(GPP_F22, 1, DEEP), // DGPU_RST#_PCH
168  //PAD_CFG_GPO(GPP_F23, 1, DEEP), // DGPU_PWR_EN
169 
170  /* ------- GPIO Group GPP_G ------- */
171  PAD_CFG_GPI(GPP_G0, UP_20K, DEEP), // BOARD_ID1
172  PAD_CFG_GPI(GPP_G1, NONE, DEEP), // BOARD_ID2
173  PAD_CFG_GPI(GPP_G2, NONE, DEEP), // TPM_DET
174  PAD_CFG_GPI(GPP_G3, NONE, DEEP), // GPIO4_1V8_MAIN_EN_R
175  PAD_CFG_GPI(GPP_G4, NONE, DEEP), // SMI#_R
176  PAD_NC(GPP_G5, NONE),
177  PAD_NC(GPP_G6, NONE),
178  PAD_NC(GPP_G7, NONE),
179 
180  /* ------- GPIO Group GPP_H ------- */
181  PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
182  PAD_NC(GPP_H1, NONE),
183  PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
184  PAD_NC(GPP_H3, NONE),
185  PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD_CLKREQ#
186  PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // SSD2_CLKREQ#
187  PAD_NC(GPP_H6, NONE),
188  PAD_NC(GPP_H7, NONE),
189  PAD_NC(GPP_H8, NONE),
190  PAD_NC(GPP_H9, NONE),
191  PAD_NC(GPP_H10, UP_20K), // SML2CLK (test point)
192  PAD_NC(GPP_H11, UP_20K), // SML2DATA (test point)
193  PAD_CFG_GPI(GPP_H12, NONE, DEEP), // GPP_H_12 (eSPI flash sharing)
194  PAD_CFG_GPI(GPP_H13, NONE, DEEP), // SML3CLK
195  PAD_NC(GPP_H14, UP_20K), // SML3DATA (test point)
196  PAD_CFG_GPI(GPP_H15, NONE, DEEP), // SML3ALERT#
197  PAD_NC(GPP_H16, UP_20K), // SML4CLK (test point)
198  PAD_NC(GPP_H17, UP_20K), // SML4DATA (test point)
199  PAD_NC(GPP_H18, UP_20K), // SML4ALERT# (test point)
200  PAD_NC(GPP_H19, NONE),
201  PAD_NC(GPP_H20, NONE),
202  PAD_NC(GPP_H21, NONE),
203  PAD_NC(GPP_H22, NONE),
204  PAD_CFG_GPI(GPP_H23, NONE, DEEP), // DGPU_SELECT#
205 
206  /* ------- GPIO Group GPP_I ------- */
207  PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), /* I_MDP_HPD on 1660 Ti,
208  NC on 1650/1650 Ti
209  */
210  PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // HDMI_HPD
211  PAD_CFG_GPI(GPP_I2, NONE, DEEP), // 1k pull to MDP_E_HPD
212  PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), // 1k pull to MDP_E_HPD
213  PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HPD
214  PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), /* I_MDP_CLK (on 1660 Ti),
215  NC (on 1650/1650 Ti)
216  */
217  PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), /* I_MDP_DATA (on 1660 Ti),
218  NC (on 1650/1650 Ti)
219  */
220  PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), /* HDMI_CTRLCLK (on 1650/1650 Ti),
221  test point (on 1660 Ti)
222  */
223  PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), /* HDMI_CTRLDATA (on 1650/1650 Ti),
224  test point (on 1660 Ti)
225  */
226  PAD_NC(GPP_I9, NONE),
227  PAD_NC(GPP_I10, NONE),
228  PAD_CFG_GPI(GPP_I11, NONE, DEEP), // 10k pull up to H_SKTOCC_N
229  PAD_NC(GPP_I12, NONE),
230  PAD_NC(GPP_I13, NONE),
231  PAD_NC(GPP_I14, NONE),
232 
233  /* ------- GPIO Group GPP_J ------- */
234  PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
235  PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2), // GPP_J1
236  PAD_NC(GPP_J2, NONE), // 100k pull down
237  PAD_NC(GPP_J3, NONE), // 100k pull down
238  PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
239  PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
240  PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
241  PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
242  PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
243  PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
244  PAD_NC(GPP_J10, NONE),
245  PAD_NC(GPP_J11, NONE), // 75k pull down
246 
247  /* ------- GPIO Group GPP_K ------- */
248  PAD_NC(GPP_K0, NONE), // PCH_GPPK0_PCH_PEXVDD_EN (test point)
249  PAD_NC(GPP_K1, NONE), // PCH_GPPK1_PCH_FBVDDQ_EN (test point)
250  PAD_NC(GPP_K2, NONE), // PCH_GPPK2_PCH_1V8RUN_EN (test point)
251  _PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x0000), // SCI#_R
252  PAD_NC(GPP_K4, NONE),
253  PAD_NC(GPP_K5, NONE),
254  _PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#_R
255  PAD_NC(GPP_K7, NONE),
256  PAD_CFG_GPO(GPP_K8, 1, DEEP), // SATA_M2_PWR_EN1
257  PAD_CFG_GPO(GPP_K9, 1, DEEP), // SATA_M2_PWR_EN2
258  PAD_NC(GPP_K10, NONE), // PCH_GPPK10_PCH_NVVDD_EN (test point)
259  PAD_NC(GPP_K11, NONE), // PCH_GPPK11_PCH_NVVDD_EN (test point)
260  PAD_NC(GPP_K12, NONE), // (test point)
261  PAD_NC(GPP_K13, NONE),
262  PAD_CFG_GPO(GPP_K14, 0, DEEP), // GPP_K14_TEST_R
263  PAD_NC(GPP_K15, NONE),
264  PAD_NC(GPP_K16, NONE), // (test point)
265  PAD_NC(GPP_K17, NONE),
266  PAD_NC(GPP_K18, NONE),
267  PAD_CFG_GPI(GPP_K19, NONE, DEEP), // SMI#_RR
268  PAD_CFG_GPO(GPP_K20, 1, DEEP), // GPU_EVENT#
269  PAD_CFG_GPI(GPP_K21, NONE, PLTRST), // GC6_FB_EN_PCH
270  PAD_CFG_GPI(GPP_K22, NONE, DEEP), // DGPU_PWRGD_R
271  PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PRSNT#
272 };
273 
275 {
277 }
#define GPD11
#define GPP_A4
#define GPP_H22
#define GPP_C15
#define GPD3
#define GPP_H20
#define GPP_B6
Definition: gpio_soc_defs.h:59
#define GPP_H19
#define GPP_D1
#define GPD9
#define GPP_C2
#define GPP_D10
#define GPP_D8
#define GPP_D17
#define GPP_E3
#define GPP_A18
#define GPP_F21
#define GPP_C12
#define GPP_F12
#define GPP_F16
#define GPP_H15
#define GPP_H16
#define GPP_E0
#define GPP_F6
#define GPP_H18
#define GPP_D14
#define GPP_B1
Definition: gpio_soc_defs.h:54
#define GPP_F20
#define GPP_C5
#define GPP_H11
#define GPP_A14
#define GPP_B12
Definition: gpio_soc_defs.h:65
#define GPP_H17
#define GPP_D12
#define GPP_B16
Definition: gpio_soc_defs.h:69
#define GPP_A5
#define GPP_B2
Definition: gpio_soc_defs.h:55
#define GPP_D7
#define GPP_B13
Definition: gpio_soc_defs.h:66
#define GPP_E6
#define GPP_F0
#define GPP_D6
#define GPP_A19
#define GPP_D2
#define GPP_H12
#define GPP_H6
#define GPP_C9
#define GPP_H2
#define GPP_C22
#define GPP_H9
#define GPD0
#define GPP_D9
#define GPP_F5
#define GPP_B15
Definition: gpio_soc_defs.h:68
#define GPP_A2
#define GPP_H21
#define GPP_C23
#define GPP_H13
#define GPP_C8
#define GPP_D11
#define GPP_H7
#define GPP_A6
#define GPP_H1
#define GPP_C11
#define GPP_H14
#define GPP_D5
#define GPP_B22
Definition: gpio_soc_defs.h:75
#define GPP_A23
#define GPP_C18
#define GPP_F9
#define GPP_C13
#define GPP_E9
#define GPP_C17
#define GPP_E8
#define GPP_A7
#define GPP_E5
#define GPP_A0
#define GPD7
#define GPP_B8
Definition: gpio_soc_defs.h:61
#define GPP_B20
Definition: gpio_soc_defs.h:73
#define GPP_A20
#define GPP_A16
#define GPP_F1
#define GPP_F17
#define GPP_A12
#define GPP_F15
#define GPP_D4
#define GPP_C10
#define GPP_C6
#define GPD2
#define GPP_F10
#define GPP_A3
#define GPP_E7
#define GPP_C16
#define GPP_F7
#define GPD1
#define GPP_F13
#define GPP_C4
#define GPP_D18
#define GPP_B19
Definition: gpio_soc_defs.h:72
#define GPP_E2
#define GPP_H0
#define GPP_H5
#define GPP_B9
Definition: gpio_soc_defs.h:62
#define GPD10
#define GPP_F14
#define GPP_H3
#define GPP_F4
#define GPP_A10
#define GPP_A8
#define GPP_D0
#define GPP_A1
#define GPP_B14
Definition: gpio_soc_defs.h:67
#define GPP_B11
Definition: gpio_soc_defs.h:64
#define GPP_D13
#define GPP_B18
Definition: gpio_soc_defs.h:71
#define GPP_B5
Definition: gpio_soc_defs.h:58
#define GPP_B0
Definition: gpio_soc_defs.h:53
#define GPP_A11
#define GPP_C14
#define GPP_A15
#define GPP_A9
#define GPP_E10
#define GPP_F8
#define GPP_C19
#define GPD8
#define GPP_A13
#define GPP_A21
#define GPP_B23
Definition: gpio_soc_defs.h:76
#define GPP_B10
Definition: gpio_soc_defs.h:63
#define GPP_D19
#define GPP_C1
#define GPP_F2
#define GPP_E11
#define GPD6
#define GPP_F18
#define GPP_B3
Definition: gpio_soc_defs.h:56
#define GPP_A22
#define GPP_D15
#define GPP_F11
#define GPP_B21
Definition: gpio_soc_defs.h:74
#define GPD4
#define GPP_B4
Definition: gpio_soc_defs.h:57
#define GPP_D16
#define GPP_F3
#define GPP_H10
#define GPP_C3
#define GPP_E12
#define GPP_A17
#define GPP_B17
Definition: gpio_soc_defs.h:70
#define GPP_E4
#define GPP_C0
#define GPD5
#define GPP_E1
#define GPP_H8
#define GPP_H4
#define GPP_H23
#define GPP_B7
Definition: gpio_soc_defs.h:60
#define GPP_C7
#define GPP_D3
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define GPP_D23
#define GPP_G1
Definition: gpio_soc_defs.h:89
#define GPP_G7
Definition: gpio_soc_defs.h:95
#define GPP_D22
#define GPP_G4
Definition: gpio_soc_defs.h:92
#define GPP_G2
Definition: gpio_soc_defs.h:90
#define GPP_D21
#define GPP_G6
Definition: gpio_soc_defs.h:94
#define GPP_G0
Definition: gpio_soc_defs.h:88
#define GPP_D20
#define GPP_G3
Definition: gpio_soc_defs.h:91
#define GPP_G5
Definition: gpio_soc_defs.h:93
#define GPP_K4
#define GPP_I12
#define GPP_I5
#define GPP_J7
#define GPP_J4
#define GPP_K2
#define GPP_K9
#define GPP_J5
#define GPP_K16
#define GPP_I10
#define GPP_K13
#define GPP_J8
#define GPP_J0
#define GPP_J2
#define GPP_J9
#define GPP_I8
#define GPP_J1
#define GPP_J6
#define GPP_K18
#define GPP_I7
#define GPP_I3
#define GPP_I6
#define GPP_J10
#define GPP_K7
#define GPP_I11
#define GPP_I9
#define GPP_K11
#define GPP_K17
#define GPP_K21
#define GPP_K20
#define GPP_K1
#define GPP_I13
#define GPP_I2
#define GPP_J11
#define GPP_J3
#define GPP_I0
#define GPP_K10
#define GPP_K5
#define GPP_K6
#define GPP_K0
#define GPP_K14
#define GPP_K12
#define GPP_I14
#define GPP_K22
#define GPP_I4
#define GPP_K3
#define GPP_I1
#define GPP_K19
#define GPP_K23
#define GPP_K15
#define GPP_K8
void variant_configure_gpios(void)
Definition: gpio.c:238
const struct pad_config gpio_table[]
Definition: gpio.c:33
void gpio_configure_pads(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
program a particular set of GPIO
Definition: gpio.c:307
#define PAD_NC(pin)
Definition: gpio_defs.h:263
#define PAD_CFG_GPI(pad, pull, rst)
Definition: gpio_defs.h:284
#define _PAD_CFG_STRUCT(__pad, __config0, __config1)
Definition: gpio_defs.h:166
#define PAD_CFG_NF(pad, pull, rst, func)
Definition: gpio_defs.h:197
#define PAD_CFG_GPO(pad, val, rst)
Definition: gpio_defs.h:247
#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst)
Definition: gpio_defs.h:402