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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <console/console.h>
#include <device/device.h>
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <cpu/intel/smm_reloc.h>
#include "chip.h"
Go to the source code of this file.
Macros | |
#define | MSR_BBL_CR_CTL3 0x11e |
#define | MSR_EMTTM_CR_TABLE(x) (0xa8 + (x)) |
#define | MSR_EMTTM_TABLE_NUM 6 |
#define | IA32_PECI_CTL 0x5a0 |
#define | PIC_SENS_CFG 0x1aa |
Functions | |
static void | configure_c_states (const int quad) |
static void | configure_p_states (const char stepping, const char cores) |
static void | configure_emttm_tables (void) |
static void | configure_misc (const int eist, const int tm2, const int emttm) |
static void | configure_pic_thermal_sensors (const int tm2, const int quad) |
static void | model_1067x_init (struct device *cpu) |
Variables | |
static struct device_operations | cpu_dev_ops |
static const struct cpu_device_id | cpu_table [] |
static const struct cpu_driver driver | __cpu_driver |
struct chip_operations | cpu_intel_model_1067x_ops |
#define IA32_PECI_CTL 0x5a0 |
Definition at line 156 of file model_1067x_init.c.
#define MSR_BBL_CR_CTL3 0x11e |
Definition at line 14 of file model_1067x_init.c.
Definition at line 107 of file model_1067x_init.c.
#define MSR_EMTTM_TABLE_NUM 6 |
Definition at line 108 of file model_1067x_init.c.
#define PIC_SENS_CFG 0x1aa |
Definition at line 209 of file model_1067x_init.c.
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Definition at line 16 of file model_1067x_init.c.
References cpu_intel_model_1067x_config::c5, cpu_intel_model_1067x_config::c6, device::chip_info, cpuid_edx(), dev_find_lapic(), msr_struct::hi, msr_struct::lo, MSR_BBL_CR_CTL3, MSR_FSB_FREQ, MSR_PKG_CST_CONFIG_CONTROL, MSR_PMG_IO_BASE_ADDR, MSR_PMG_IO_CAPTURE_ADDR, NULL, PMB0_BASE, PMB1_BASE, rdmsr(), SPEEDSTEP_APIC_MAGIC, and wrmsr().
Definition at line 109 of file model_1067x_init.c.
References BIOS_DEBUG, sst_state_t::dynfsb, msr_struct::hi, sst_state_t::is_slfm, sst_state_t::is_turbo, msr_struct::lo, MSR_EMTTM_CR_TABLE, MSR_EMTTM_TABLE_NUM, sst_state_t::nonint, sst_table_t::num_states, sst_state_t::power, printk, sst_state_t::ratio, rdmsr(), SPEEDSTEP_ENCODE_STATE, speedstep_gen_pstates(), SPEEDSTEP_RATIO_NONINT, sst_table_t::states, sst_state_t::vid, and wrmsr().
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Definition at line 158 of file model_1067x_init.c.
References cpuid_edx(), msr_struct::hi, IA32_MISC_ENABLE, IA32_PECI_CTL, msr_struct::lo, MSR_FSB_CLOCK_VCC, rdmsr(), and wrmsr().
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Definition at line 74 of file model_1067x_init.c.
References device::chip_info, dev_find_lapic(), msr_struct::hi, IA32_PERF_CTL, msr_struct::lo, MSR_EXTENDED_CONFIG, MSR_FSB_CLOCK_VCC, MSR_FSB_FREQ, MSR_PKG_CST_CONFIG_CONTROL, NULL, rdmsr(), cpu_intel_model_1067x_config::slfm, SPEEDSTEP_APIC_MAGIC, stepping, and wrmsr().
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Definition at line 210 of file model_1067x_init.c.
References msr_struct::lo, PIC_SENS_CFG, rdmsr(), and wrmsr().
Definition at line 228 of file model_1067x_init.c.
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Definition at line 228 of file model_1067x_init.c.
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Definition at line 228 of file model_1067x_init.c.
struct chip_operations cpu_intel_model_1067x_ops |
Definition at line 228 of file model_1067x_init.c.
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Definition at line 228 of file model_1067x_init.c.