coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <
commonlib/helpers.h
>
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static
const
struct
pad_config
gpio_table
[] = {
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/* A8 : PEN_GARAGE_DET_L (wake) */
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PAD_CFG_GPI_SCI
(
GPP_A8
,
NONE
, DEEP, EDGE_SINGLE,
NONE
),
10
/* A10 : FPMCU_PCH_BOOT1 */
11
PAD_CFG_GPO
(
GPP_A10
, 0, DEEP),
12
/* A18 : ISH_GP0 ==> NC */
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PAD_NC
(
GPP_A18
,
NONE
),
14
/* A19 : ISH_GP1 ==> NC */
15
PAD_NC
(
GPP_A19
,
NONE
),
16
/* A20 : ISH_GP2 ==> NC */
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PAD_NC
(
GPP_A20
,
NONE
),
18
/* A22 : ISH_GP4 ==> NC */
19
PAD_NC
(
GPP_A22
,
NONE
),
20
/* A23 : ISH_GP5 ==> NC */
21
PAD_NC
(
GPP_A23
,
NONE
),
22
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/* B19 : GSPI1_CS0# ==> NC */
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PAD_NC
(
GPP_B19
,
NONE
),
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/* B20 : GSPI1_CLK ==> NC */
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PAD_NC
(
GPP_B20
,
NONE
),
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/* B21 : GSPI1_MISO ==> NC */
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PAD_NC
(
GPP_B21
,
NONE
),
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/* B22 : GSPI1_MOSI ==> NC */
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PAD_NC
(
GPP_B22
,
NONE
),
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/* C1 : SMBDATA ==> NC */
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PAD_NC
(
GPP_C1
,
NONE
),
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/* C4 : TOUCHSCREEN_DIS_L */
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PAD_CFG_GPO
(
GPP_C4
, 0, DEEP),
36
/* C7 : GPP_C7 ==> Touchscreen_INT_L */
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PAD_CFG_GPI_APIC
(
GPP_C7
,
NONE
, PLTRST, LEVEL, INVERT),
38
/* C11 : UART0_CTS# ==> NC */
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PAD_NC
(
GPP_C11
,
NONE
),
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/* C23 : UART2_CTS# ==> NC */
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PAD_NC
(
GPP_C23
,
NONE
),
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/* D4 : USI_BASE_REPORT_EN */
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PAD_CFG_GPO
(
GPP_D4
, 0, DEEP),
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/* D10 : GPP_D10 ==> EN_PP3300_DX_BASE_TOUCHSCREEN */
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PAD_CFG_GPO
(
GPP_D10
, 0, DEEP),
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/* D16 : USI_INT_L */
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PAD_CFG_GPI_APIC
(
GPP_D16
,
NONE
, PLTRST, LEVEL, INVERT),
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/* F0 : GPP_F0 ==> NC */
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PAD_NC
(
GPP_F0
,
NONE
),
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/* F1 : GPP_F1 ==> NC */
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PAD_NC
(
GPP_F1
,
NONE
),
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/* F3 : GPP_F3 ==> MEM_STRAP_3 */
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PAD_CFG_GPI
(
GPP_F3
,
NONE
, PLTRST),
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/* F10 : GPP_F10 ==> MEM_STRAP_2 */
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PAD_CFG_GPI
(
GPP_F10
,
NONE
, PLTRST),
58
/* F11 : EMMC_CMD ==> NC */
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PAD_NC
(
GPP_F11
,
NONE
),
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/* F20 : EMMC_RCLK ==> NC */
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PAD_NC
(
GPP_F20
,
NONE
),
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/* F21 : EMMC_CLK ==> NC */
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PAD_NC
(
GPP_F21
,
NONE
),
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/* F22 : EMMC_RESET# ==> NC */
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PAD_NC
(
GPP_F22
,
NONE
),
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/* G0 : GPP_G0 ==> NC */
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PAD_NC
(
GPP_G0
,
NONE
),
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/* G1 : GPP_G1 ==> NC */
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PAD_NC
(
GPP_G1
,
NONE
),
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/* G2 : GPP_G2 ==> NC */
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PAD_NC
(
GPP_G2
,
NONE
),
73
/* G3 : GPP_G3 ==> NC */
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PAD_NC
(
GPP_G3
,
NONE
),
75
/* G4 : GPP_G4 ==> NC */
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PAD_NC
(
GPP_G4
,
NONE
),
77
/* G5 : GPP_G5 ==> NC */
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PAD_NC
(
GPP_G5
,
NONE
),
79
/* G6 : GPP_G6 ==> NC */
80
PAD_NC
(
GPP_G6
,
NONE
),
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/* H3 : SPKR_PA_EN */
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PAD_CFG_GPO
(
GPP_H3
, 1, DEEP),
84
/* H4 : Touchscreen I2C2_SDA */
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PAD_CFG_NF
(
GPP_H4
,
NONE
, DEEP, NF1),
86
/* H5 : Touchscreen I2C2_SCL */
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PAD_CFG_NF
(
GPP_H5
,
NONE
, DEEP, NF1),
88
/* H13 : M2_SKT2_CFG1 ==> SPKR_RST_L */
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PAD_CFG_GPO
(
GPP_H13
, 1, DEEP),
90
/* H14 : M2_SKT2_CFG2 ==> TOUCHSCREEN_STOP_L */
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PAD_CFG_GPO
(
GPP_H14
, 1, PLTRST),
92
/* H19 : TIMESYNC[0] ==> MEM_STRAP_0 */
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PAD_CFG_GPI
(
GPP_H19
,
NONE
, PLTRST),
94
/* H22 : MEM_STRAP_1 */
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PAD_CFG_GPI
(
GPP_H22
,
NONE
, PLTRST),
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};
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const
struct
pad_config
*
override_gpio_table
(
size_t
*num)
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{
100
*num =
ARRAY_SIZE
(
gpio_table
);
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return
gpio_table
;
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}
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/*
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* GPIOs configured before ramstage
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* Note: the Hatch platform's romstage will configure
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* the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins
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* as inputs before it reads them, so they are not
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* needed in this table.
110
*/
111
static
const
struct
pad_config
early_gpio_table
[] = {
112
/* B15 : H1_SLAVE_SPI_CS_L */
113
PAD_CFG_NF
(
GPP_B15
,
NONE
, DEEP, NF1),
114
/* B16 : H1_SLAVE_SPI_CLK */
115
PAD_CFG_NF
(
GPP_B16
,
NONE
, DEEP, NF1),
116
/* B17 : H1_SLAVE_SPI_MISO_R */
117
PAD_CFG_NF
(
GPP_B17
,
NONE
, DEEP, NF1),
118
/* B18 : H1_SLAVE_SPI_MOSI_R */
119
PAD_CFG_NF
(
GPP_B18
,
NONE
, DEEP, NF1),
120
/* C8 : UART_PCH_RX_DEBUG_TX */
121
PAD_CFG_NF
(
GPP_C8
,
NONE
, DEEP, NF1),
122
/* C9 : UART_PCH_TX_DEBUG_RX */
123
PAD_CFG_NF
(
GPP_C9
,
NONE
, DEEP, NF1),
124
/* C14 : BT_DISABLE_L */
125
PAD_CFG_GPO
(
GPP_C14
, 0, DEEP),
126
/* PCH_WP_OD */
127
PAD_CFG_GPI
(
GPP_C20
,
NONE
, DEEP),
128
/* C21 : H1_PCH_INT_ODL */
129
PAD_CFG_GPI_APIC
(
GPP_C21
,
NONE
, PLTRST, LEVEL, INVERT),
130
/* C22 : EC_IN_RW_OD */
131
PAD_CFG_GPI
(
GPP_C22
,
NONE
, DEEP),
132
/* E1 : M2_SSD_PEDET */
133
PAD_CFG_NF
(
GPP_E1
,
NONE
, DEEP, NF1),
134
/* E5 : SATA_DEVSLP1 */
135
PAD_CFG_NF
(
GPP_E5
,
NONE
, PLTRST, NF1),
136
/* F2 : MEM_CH_SEL */
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PAD_CFG_GPI
(
GPP_F2
,
NONE
, PLTRST),
138
};
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const
struct
pad_config
*
variant_early_gpio_table
(
size_t
*num)
141
{
142
*num =
ARRAY_SIZE
(
early_gpio_table
);
143
return
early_gpio_table
;
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}
GPP_H22
#define GPP_H22
Definition:
gpio_soc_defs.h:238
GPP_H19
#define GPP_H19
Definition:
gpio_soc_defs.h:235
GPP_D10
#define GPP_D10
Definition:
gpio_soc_defs.h:262
GPP_A18
#define GPP_A18
Definition:
gpio_soc_defs.h:137
GPP_F21
#define GPP_F21
Definition:
gpio_soc_defs.h:594
GPP_F20
#define GPP_F20
Definition:
gpio_soc_defs.h:593
GPP_B16
#define GPP_B16
Definition:
gpio_soc_defs.h:69
GPP_F0
#define GPP_F0
Definition:
gpio_soc_defs.h:573
GPP_A19
#define GPP_A19
Definition:
gpio_soc_defs.h:138
GPP_C9
#define GPP_C9
Definition:
gpio_soc_defs.h:546
GPP_C22
#define GPP_C22
Definition:
gpio_soc_defs.h:559
GPP_B15
#define GPP_B15
Definition:
gpio_soc_defs.h:68
GPP_C23
#define GPP_C23
Definition:
gpio_soc_defs.h:560
GPP_H13
#define GPP_H13
Definition:
gpio_soc_defs.h:229
GPP_C8
#define GPP_C8
Definition:
gpio_soc_defs.h:545
GPP_C11
#define GPP_C11
Definition:
gpio_soc_defs.h:548
GPP_H14
#define GPP_H14
Definition:
gpio_soc_defs.h:230
GPP_B22
#define GPP_B22
Definition:
gpio_soc_defs.h:75
GPP_A23
#define GPP_A23
Definition:
gpio_soc_defs.h:142
GPP_E5
#define GPP_E5
Definition:
gpio_soc_defs.h:633
GPP_C20
#define GPP_C20
Definition:
gpio_soc_defs.h:557
GPP_B20
#define GPP_B20
Definition:
gpio_soc_defs.h:73
GPP_A20
#define GPP_A20
Definition:
gpio_soc_defs.h:139
GPP_F1
#define GPP_F1
Definition:
gpio_soc_defs.h:574
GPP_D4
#define GPP_D4
Definition:
gpio_soc_defs.h:256
GPP_F10
#define GPP_F10
Definition:
gpio_soc_defs.h:583
GPP_C4
#define GPP_C4
Definition:
gpio_soc_defs.h:541
GPP_B19
#define GPP_B19
Definition:
gpio_soc_defs.h:72
GPP_H5
#define GPP_H5
Definition:
gpio_soc_defs.h:221
GPP_C21
#define GPP_C21
Definition:
gpio_soc_defs.h:558
GPP_H3
#define GPP_H3
Definition:
gpio_soc_defs.h:219
GPP_A10
#define GPP_A10
Definition:
gpio_soc_defs.h:129
GPP_A8
#define GPP_A8
Definition:
gpio_soc_defs.h:127
GPP_B18
#define GPP_B18
Definition:
gpio_soc_defs.h:71
GPP_C14
#define GPP_C14
Definition:
gpio_soc_defs.h:551
GPP_C1
#define GPP_C1
Definition:
gpio_soc_defs.h:538
GPP_F2
#define GPP_F2
Definition:
gpio_soc_defs.h:575
GPP_A22
#define GPP_A22
Definition:
gpio_soc_defs.h:141
GPP_F22
#define GPP_F22
Definition:
gpio_soc_defs.h:595
GPP_F11
#define GPP_F11
Definition:
gpio_soc_defs.h:584
GPP_B21
#define GPP_B21
Definition:
gpio_soc_defs.h:74
GPP_D16
#define GPP_D16
Definition:
gpio_soc_defs.h:268
GPP_F3
#define GPP_F3
Definition:
gpio_soc_defs.h:576
GPP_B17
#define GPP_B17
Definition:
gpio_soc_defs.h:70
GPP_E1
#define GPP_E1
Definition:
gpio_soc_defs.h:629
GPP_H4
#define GPP_H4
Definition:
gpio_soc_defs.h:220
GPP_C7
#define GPP_C7
Definition:
gpio_soc_defs.h:544
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
GPP_G1
#define GPP_G1
Definition:
gpio_soc_defs.h:89
GPP_G4
#define GPP_G4
Definition:
gpio_soc_defs.h:92
GPP_G2
#define GPP_G2
Definition:
gpio_soc_defs.h:90
GPP_G6
#define GPP_G6
Definition:
gpio_soc_defs.h:94
GPP_G0
#define GPP_G0
Definition:
gpio_soc_defs.h:88
GPP_G3
#define GPP_G3
Definition:
gpio_soc_defs.h:91
GPP_G5
#define GPP_G5
Definition:
gpio_soc_defs.h:93
helpers.h
variant_early_gpio_table
const struct pad_config * variant_early_gpio_table(size_t *num)
Definition:
gpio.c:204
override_gpio_table
const struct pad_config * override_gpio_table(size_t *num)
Definition:
gpio.c:124
gpio_table
static const struct pad_config gpio_table[]
Definition:
gpio.c:7
early_gpio_table
static const struct pad_config early_gpio_table[]
Definition:
gpio.c:111
NONE
@ NONE
Definition:
qup_se_handlers_common.h:196
PAD_NC
#define PAD_NC(pin)
Definition:
gpio_defs.h:263
PAD_CFG_GPI
#define PAD_CFG_GPI(pad, pull, rst)
Definition:
gpio_defs.h:284
PAD_CFG_NF
#define PAD_CFG_NF(pad, pull, rst, func)
Definition:
gpio_defs.h:197
PAD_CFG_GPI_APIC
#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv)
Definition:
gpio_defs.h:376
PAD_CFG_GPO
#define PAD_CFG_GPO(pad, val, rst)
Definition:
gpio_defs.h:247
PAD_CFG_GPI_SCI
#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv)
Definition:
gpio_defs.h:432
pad_config
Definition:
gpio.h:75
src
mainboard
google
hatch
variants
palkia
gpio.c
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