raminit.h File Reference

#include "ironlake.h"

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Data Structures
struct	timing_bounds_t
struct	ram_training
struct	raminfo

Macros
#define	NUM_CHANNELS   2
#define	NUM_SLOTS   2
#define	NUM_RANKS   2
#define	MRC_CACHE_VERSION   3

Functions
static unsigned int	fsbcycle_ps (struct raminfo *info)
static unsigned int	halfcycle_ps (struct raminfo *info)
static unsigned int	frequency_11 (struct raminfo *info)
void	chipset_init (const int s3resume)
void	raminit (const int s3resume, const u8 *spd_addrmap)
u16	get_max_timing (struct raminfo *info, int channel)
void	early_quickpath_init (struct raminfo *info, const u8 x2ca8)
void	late_quickpath_init (struct raminfo *info, const int s3resume)

Macro Definition Documentation

MRC_CACHE_VERSION

#define MRC_CACHE_VERSION   3

Definition at line 18 of file raminit.h.

NUM_CHANNELS

#define NUM_CHANNELS   2

Definition at line 8 of file raminit.h.

NUM_RANKS

#define NUM_RANKS   2

Definition at line 10 of file raminit.h.

NUM_SLOTS

#define NUM_SLOTS   2

Definition at line 9 of file raminit.h.

Function Documentation

chipset_init()

void chipset_init

(

const int

s3resume

)

Definition at line 2860 of file raminit.c.

References BIOS_DEBUG, DEVEN, dmi_setup(), gav, get_uint_option(), GGC, GMA, mchbar_clrsetbits32(), mchbar_clrsetbits8(), mchbar_read8(), mchbar_setbits16, mchbar_write16(), mchbar_write8(), MSAC, NORTHBRIDGE, pci_read_config16(), pci_read_config8(), pci_write_config16(), pci_write_config8(), printk, RCBA32, RCBA8, and system_reset().

Referenced by mainboard_romstage_entry().

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early_quickpath_init()

void early_quickpath_init	(	struct raminfo *	info,
		const u8	x2ca8
	)

Definition at line 476 of file quickpath.c.

References info, msr_struct::lo, mchbar_clrbits32, mchbar_clrsetbits32(), mchbar_clrsetbits8(), mchbar_read32(), mchbar_setbits32, mchbar_setbits8, mchbar_write16(), mchbar_write32(), MIRROR_PORT_CTL, MSR_TURBO_POWER_CURRENT_LIMIT, pci_read_config32(), pci_update_config32(), pci_write_config32(), QPI_DEF_RMT_VN_CREDITS, QPI_LINK_0, QPI_NON_CORE, QPI_PHY_0, QPI_PHY_CONTROL, QPI_PHY_EP_MCTR, QPI_PHY_EP_SELECT, QPI_PHY_PRIM_TIMEOUT, QPI_PHY_PWR_MGMT, QPI_QPILCL, quickpath_configure_pll_ratio(), and rdmsr().

Referenced by raminit().

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frequency_11()

static unsigned int frequency_11 ( struct raminfo *  info )

inlinestatic

Definition at line 90 of file raminit.h.

References info.

Referenced by compute_274265(), frequency_01(), ns_to_cycles(), program_board_delay(), ps_to_halfcycles(), and set_2dxx_series().

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fsbcycle_ps()

static unsigned int fsbcycle_ps ( struct raminfo *  info )

inlinestatic

Definition at line 78 of file raminit.h.

References info.

Referenced by compute_274265(), and program_board_delay().

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get_max_timing()

u16 get_max_timing	(	struct raminfo *	info,
		int	channel
	)

Definition at line 2824 of file raminit.c.

References get_timing_register_addr(), info, MAX, mchbar_read8(), NUM_RANKS, NUM_SLOTS, and read_500().

Referenced by compute_274265().

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halfcycle_ps()

static unsigned int halfcycle_ps ( struct raminfo *  info )

inlinestatic

Definition at line 84 of file raminit.h.

References info.

Referenced by compute_274265(), compute_derived_timings(), cycle_ps(), and program_board_delay().

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late_quickpath_init()

void late_quickpath_init	(	struct raminfo *	info,
		const int	s3resume
	)

Definition at line 592 of file quickpath.c.

References compute_274265(), DEVEN, info, mchbar_clrbits32, mchbar_clrsetbits16(), mchbar_clrsetbits32(), mchbar_read8(), mchbar_setbits32, mchbar_write16(), mchbar_write32(), mchbar_write8(), NORTHBRIDGE, PCI_DEV, pci_read_config16(), pci_read_config8(), program_274265(), set_2dxx_series(), and udelay().

Referenced by raminit().

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raminit()

void raminit	(	const int	s3resume,
		const u8 *	spd_addrmap
	)

Definition at line 2919 of file raminit.c.

References addr, ARRAY_SIZE, BIOS_DEBUG, BIOS_ERR, BIOS_INFO, calculate_timings(), CAPID0, CAS_LATENCIES_LSB, CAS_LATENCIES_MSB, CAS_LATENCY_TIME, cbmem_recovery(), collect_system_info(), compute_derived_timings(), config_rank(), CYCLETIME, DEFAULT_PMBASE, DENSITY, DEVICE_TYPE, die(), dump_timings(), early_quickpath_init(), epbar_read32(), epbar_write32(), EPVC1RCAP, full_reset(), gav, GEN_PMCON_2, get_bits_420(), get_cached_training(), get_lane_offset(), get_timing_register_addr(), halt(), have_match_ranks(), info, inl(), intel_early_me_init(), intel_early_me_uma_size(), IOMMU_BASE1, IOMMU_BASE2, IOMMU_BASE4, jedec_init(), jedec_read(), late_quickpath_init(), MAX_RTIDS, mchbar_clrbits16, mchbar_clrbits32, mchbar_clrbits8, mchbar_clrsetbits32(), mchbar_clrsetbits8(), mchbar_read16(), mchbar_read32(), mchbar_read8(), mchbar_setbits16, mchbar_setbits32, mchbar_setbits8, mchbar_write16(), mchbar_write32(), mchbar_write8(), MEMORY_BUS_WIDTH, memset(), MiB, MODULE_TYPE, NORTHBRIDGE, NULL, NUM_CHANNELS, NUM_RANKS, NUM_SLOTS, outl(), pci_read_config16(), pci_read_config32(), pci_read_config8(), pci_write_config16(), pci_write_config32(), pci_write_config8(), PM1_CNT, raminfo::populated_ranks, printk, program_base_timings(), program_board_delay(), program_modules_memory_map(), program_total_memory_map(), QPI_NON_CORE, ram_check_nodie(), RAM_DEBUG, ram_training(), RANK1_ADDRESS_MAPPING, RANKS_AND_DQ, rdmsr(), read8(), read_1d0(), read_pmbase32(), REFERENCE_RAW_CARD_USED, rmw_1d0(), rmw_500(), save_timings(), set_334(), set_4cf(), setup_heci_uma(), SLP_TYP_S3, smbus_read_byte(), SOUTHBRIDGE, raminfo::spd, system_reset(), THERMAL_AND_REFRESH, TIMEBASE_DIVIDEND, TIMEBASE_DIVISOR, timestamp_add_now(), TOM, udelay(), value, write32p(), write_1d0(), write_26c(), write_500(), and write_pmbase32().

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