36 }
while ((
val | tmp) !=
val);
static void write32(void *addr, uint32_t val)
static uint32_t read32(const void *addr)
void clock_init_dp_clock(void)
void system_clock_init(struct mem_timings *mem, struct arm_clk_ratios *arm_clk_ratio)
static struct exynos5_mct *const exynos_mct
static struct exynos5_clock *const exynos_clock
#define MUX_MCLK_CDREX_SEL
#define CLK_SMMU_SCALERP_MASK
#define CLK_DIV_SYSRGT_VAL
#define CLK_SMMUFIMC_LITE1_MASK
#define CLK_SMMURTIC_MASK
#define CLK_DIV_PERIC2_VAL
#define CLK_SMMU3DNR_MASK
#define CLK_I2C0_ISP_MASK
#define MMC3_PRE_RATIO_OFFSET
#define set_pll(mdiv, pdiv, sdiv)
#define CLK_TZASC_DRBXR_MASK
#define MUX_GPLL_SEL_MASK
#define CLK_DIV_CORE1_VAL
#define MMC2_RATIO_OFFSET
#define CLK_SMMU_SCALERC_MASK
#define CLK_GATE_DP1_ALLOW
#define CLK_SATA_PHY_I2C_MASK
#define CLK_MPWM_ISP_MASK
#define CLK_I2C1_ISP_MASK
#define CLK_SMMUROTATOR_MASK
#define CLK_INT_COMB_ISP_MASK
#define SCLK_MPWM_ISP_MASK
#define CLK_SMMU_MCUISP_MASK
#define CLK_SMMUMFCR_MASK
#define MUX_CPLL_SEL_MASK
#define MMC3_RATIO_OFFSET
#define CLK_SMMUJPEG_MASK
#define MMC2_PRE_RATIO_OFFSET
#define CLK_SMMUDIS1_MASK
#define CLK_ID_REMAPPER_MASK
#define CLK_SPI0_ISP_MASK
#define MUX_VPLL_SEL_MASK
#define CLK_SPI1_ISP_MASK
#define CLK_SRC_CORE1_VAL
#define CLK_DIV_SYSLFT_VAL
#define CLK_SMMU_ISP_MASK
#define HPM_SEL_SCLK_MPLL
#define CLK_SRC_CORE0_VAL
#define CLK_SMMUMDMA_MASK
#define MMC3_PRE_RATIO_VAL
#define CLK_SMMUGSCL2_MASK
#define CLK_SMMUGSCL3_MASK
#define MUX_APLL_SEL_MASK
#define CLK_SMMUDIS0_MASK
#define CLK_DIV_CDREX_VAL
#define CLK_ASYNCTVX_MASK
#define MUX_BPLL_SEL_MASK
#define CLK_SMMUMDMA1_MASK
#define CLK_DIV_PERIC1_VAL
#define CLK_MTCADC_ISP_MASK
#define CLK_DIV_FSYS0_VAL
#define CLK_SMMUFIMC_LITE0_MASK
#define CLK_SMMUGSCL0_MASK
#define CLK_SMMUMFCL_MASK
#define CLK_SRC_FSYS0_VAL
#define MUX_MPLL_SEL_MASK
#define CLK_SMMUMCU_IOP_MASK
#define CLK_DIV_PERIC0_VAL
#define MUX_EPLL_SEL_MASK
#define CLK_SMMUGSCL1_MASK
#define CLK_CAMIF_TOP_MASK
#define CLK_DIV_DISP1_0_FIMD1
#define CLK_SMMUFIMC_LITE2_MASK
#define CLK_UART_ISP_MASK
#define CLK_DIV_CORE0_VAL
#define CLK_SRC_DISP1_0_VAL
#define CLK_MIPI_HSI_MASK
#define MMC2_PRE_RATIO_VAL
#define CLK_SATA_PHY_CTRL_MASK
#define MUX_BPLL_FOUT_SEL
#define CLK_SMMU_DRC_MASK
#define CLK_MCUCTL_ISP_MASK
#define MUX_MPLL_FOUT_SEL
#define CLK_SRC_PERIC1_VAL
#define CLK_SRC_PERIC0_VAL
#define CLK_GSCL_WRAP_B_MASK
#define CLK_GSCL_WRAP_A_MASK
#define MUX_MCLK_DPHY_SEL
#define setbits32(addr, set)
#define clrbits32(addr, clear)
unsigned int periph_ratio
unsigned int pclk_dbg_ratio
unsigned int gate_ip_isp1
unsigned int div_stat_top0
unsigned int mux_stat_cpu
unsigned int gate_ip_gscl
unsigned int div_stat_acp
unsigned int gate_ip_peric
unsigned int gate_ip_cdrex
unsigned int div_stat_r0x
unsigned int sclk_div_isp
unsigned int clkout_cmu_cpu
unsigned int gate_ip_fsys
unsigned int mux_stat_cdrex
unsigned int div_stat_fsys0
unsigned int gate_sclk_isp
unsigned int sclk_src_isp
unsigned int clkout_cmu_r1x
unsigned int clkout_cmu_core
unsigned int mux_stat_core1
unsigned int gate_ip_peris
unsigned int mux_stat_top2
unsigned int div_stat_r1x
unsigned int gate_ip_isp0
unsigned int div_stat_cpu0
unsigned int div_stat_syslft
unsigned int div_stat_lex
unsigned int clkout_cmu_cdrex
unsigned int clkout_cmu_top
unsigned int div_stat_top1
unsigned int clkout_cmu_lex
unsigned int gate_ip_sysrgt
unsigned int gate_ip_disp1
unsigned int div_stat_sysrgt
unsigned int gate_bus_syslft
unsigned int mux_stat_lex
unsigned int div_stat_cpu1
unsigned int clkout_cmu_acp
unsigned int clkout_cmu_r0x
unsigned int div_stat_core0
unsigned int div_stat_cdrex
unsigned int pll_div2_sel
unsigned int div_stat_core1