coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
Functions
clock_init.c File Reference
#include <device/mmio.h>
#include <soc/clk.h>
#include <soc/dp.h>
#include <soc/setup.h>
Include dependency graph for clock_init.c:

Go to the source code of this file.

Functions

void system_clock_init (struct mem_timings *mem, struct arm_clk_ratios *arm_clk_ratio)
 
void clock_gate (void)
 
void clock_init_dp_clock (void)
 

Function Documentation

◆ clock_gate()

void clock_gate ( void  )

Definition at line 267 of file clock_init.c.

References CLK_3DNR_MASK, CLK_AC97_MASK, CLK_ACP_MASK, CLK_ARM9S_MASK, CLK_ASYNCTVX_MASK, CLK_C2C_MASK, CLK_CAMIF_TOP_MASK, CLK_DIS_MASK, CLK_DPHY0_MASK, CLK_DPHY1_MASK, CLK_DRC_MASK, CLK_DSIM1_MASK, CLK_EFCLK_MASK, CLK_FD_MASK, CLK_G2D_MASK, CLK_GICISP_MASK, CLK_GSCL0_MASK, CLK_GSCL1_MASK, CLK_GSCL2_MASK, CLK_GSCL3_MASK, CLK_GSCL_WRAP_A_MASK, CLK_GSCL_WRAP_B_MASK, CLK_HDMI_MASK, CLK_HS_I2C0_MASK, CLK_HS_I2C1_MASK, CLK_HS_I2C2_MASK, CLK_HS_I2C3_MASK, CLK_I2C0_ISP_MASK, CLK_I2C1_ISP_MASK, CLK_I2S2_MASK, CLK_ID_REMAPPER_MASK, CLK_INT_COMB_ISP_MASK, CLK_ISP_MASK, CLK_JPEG_MASK, CLK_MCU_IOP_MASK, CLK_MCUCTL_ISP_MASK, CLK_MCUCTL_MASK, CLK_MCUISP_MASK, CLK_MDMA1_MASK, CLK_MDMA_MASK, CLK_MFC_MASK, CLK_MIPI_HSI_MASK, CLK_MIXER_MASK, CLK_MPWM_ISP_MASK, CLK_MTCADC_ISP_MASK, CLK_NFCON_MASK, CLK_ODC_MASK, CLK_PCM1_MASK, CLK_PCM2_MASK, CLK_PDMA0_MASK, CLK_PDMA1_MASK, CLK_PWM_ISP_MASK, CLK_ROTATOR_MASK, CLK_RTC_MASK, CLK_RTIC_MASK, CLK_SATA_MASK, CLK_SATA_PHY_CTRL_MASK, CLK_SATA_PHY_I2C_MASK, CLK_SCALERC_MASK, CLK_SCALERP_MASK, CLK_SECJTAG_MASK, CLK_SMMU3DNR_MASK, CLK_SMMU_DRC_MASK, CLK_SMMU_FD_MASK, CLK_SMMU_ISP_MASK, CLK_SMMU_MCUISP_MASK, CLK_SMMU_SCALERC_MASK, CLK_SMMU_SCALERP_MASK, CLK_SMMUDIS0_MASK, CLK_SMMUDIS1_MASK, CLK_SMMUFIMC_LITE0_MASK, CLK_SMMUFIMC_LITE1_MASK, CLK_SMMUFIMC_LITE2_MASK, CLK_SMMUG2D_MASK, CLK_SMMUGSCL0_MASK, CLK_SMMUGSCL1_MASK, CLK_SMMUGSCL2_MASK, CLK_SMMUGSCL3_MASK, CLK_SMMUJPEG_MASK, CLK_SMMUMCU_IOP_MASK, CLK_SMMUMDMA1_MASK, CLK_SMMUMDMA_MASK, CLK_SMMUMFCL_MASK, CLK_SMMUMFCR_MASK, CLK_SMMUODC_MASK, CLK_SMMUROTATOR_MASK, CLK_SMMURTIC_MASK, CLK_SMMUSSS_MASK, CLK_SMMUTVX_MASK, CLK_SPDIF_MASK, CLK_SPI0_ISP_MASK, CLK_SPI0_MASK, CLK_SPI1_ISP_MASK, CLK_SPI2_MASK, CLK_SSS_MASK, CLK_TZASC_DRBXR_MASK, CLK_TZPC0_MASK, CLK_TZPC1_MASK, CLK_TZPC2_MASK, CLK_TZPC3_MASK, CLK_TZPC4_MASK, CLK_TZPC5_MASK, CLK_TZPC6_MASK, CLK_TZPC7_MASK, CLK_TZPC8_MASK, CLK_TZPC9_MASK, CLK_UART_ISP_MASK, CLK_USBOTG_MASK, CLK_WDT_IOP_MASK, CLK_WDT_ISP_MASK, clrbits32, exynos_clock, exynos5_clock::gate_block, exynos5_clock::gate_bus_syslft, exynos5_clock::gate_ip_acp, exynos5_clock::gate_ip_cdrex, exynos5_clock::gate_ip_disp1, exynos5_clock::gate_ip_fsys, exynos5_clock::gate_ip_gen, exynos5_clock::gate_ip_gscl, exynos5_clock::gate_ip_isp0, exynos5_clock::gate_ip_isp1, exynos5_clock::gate_ip_mfc, exynos5_clock::gate_ip_peric, exynos5_clock::gate_ip_peris, exynos5_clock::gate_ip_sysrgt, exynos5_clock::gate_sclk_isp, and SCLK_MPWM_ISP_MASK.

Referenced by mainboard_init().

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◆ clock_init_dp_clock()

void clock_init_dp_clock ( void  )

Definition at line 417 of file clock_init.c.

References CLK_DIV_DISP1_0_FIMD1, CLK_GATE_DP1_ALLOW, exynos5_clock::div_disp1_0, exynos_clock, exynos5_clock::gate_ip_disp1, and setbits32.

Referenced by dp_controller_init().

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◆ system_clock_init()

void system_clock_init ( struct mem_timings *  mem,
struct arm_clk_ratios *  arm_clk_ratio 
)

Definition at line 10 of file clock_init.c.

References arm_clk_ratios::acp_ratio, exynos5_clock::apll_con0, APLL_CON0_LOCKED, exynos5_clock::apll_con1, APLL_CON1_VAL, APLL_FOUT, exynos5_clock::apll_lock, APLL_LOCK_VAL, arm_clk_ratios::apll_mdiv, arm_clk_ratios::apll_pdiv, arm_clk_ratios::apll_ratio, arm_clk_ratios::apll_sdiv, arm_clk_ratios::arm2_ratio, arm_clk_ratios::arm_ratio, arm_clk_ratios::atb_ratio, exynos5_clock::bpll_con0, BPLL_CON0_LOCKED, exynos5_clock::bpll_con1, BPLL_CON1_VAL, exynos5_clock::bpll_lock, BPLL_LOCK_VAL, mem_timings::bpll_mdiv, mem_timings::bpll_pdiv, mem_timings::bpll_sdiv, CLK_DIV_ACP_VAL, CLK_DIV_CDREX_VAL, CLK_DIV_CORE0_VAL, CLK_DIV_CORE1_VAL, CLK_DIV_CPU1_VAL, CLK_DIV_FSYS0_VAL, CLK_DIV_ISP0_VAL, CLK_DIV_ISP1_VAL, CLK_DIV_ISP2_VAL, CLK_DIV_LEX_VAL, CLK_DIV_PERIC0_VAL, CLK_DIV_PERIC1_VAL, CLK_DIV_PERIC2_VAL, CLK_DIV_R0X_VAL, CLK_DIV_R1X_VAL, CLK_DIV_SYSLFT_VAL, CLK_DIV_SYSRGT_VAL, CLK_DIV_TOP0_VAL, CLK_DIV_TOP1_VAL, CLK_REG_DISABLE, CLK_SRC_CORE0_VAL, CLK_SRC_CORE1_VAL, CLK_SRC_CPU_VAL, CLK_SRC_DISP1_0_VAL, CLK_SRC_FSYS0_VAL, CLK_SRC_LEX_VAL, CLK_SRC_PERIC0_VAL, CLK_SRC_PERIC1_VAL, CLK_SRC_TOP0_VAL, CLK_SRC_TOP1_VAL, CLK_SRC_TOP2_VAL, CLK_SRC_TOP3_VAL, exynos5_clock::clkout_cmu_acp, exynos5_clock::clkout_cmu_cdrex, exynos5_clock::clkout_cmu_core, exynos5_clock::clkout_cmu_cpu, exynos5_clock::clkout_cmu_lex, exynos5_clock::clkout_cmu_r0x, exynos5_clock::clkout_cmu_r1x, exynos5_clock::clkout_cmu_top, clrbits32, exynos5_clock::cpll_con0, CPLL_CON0_LOCKED, exynos5_clock::cpll_con1, CPLL_CON1_VAL, exynos5_clock::cpll_lock, CPLL_LOCK_VAL, mem_timings::cpll_mdiv, mem_timings::cpll_pdiv, mem_timings::cpll_sdiv, arm_clk_ratios::cpud_ratio, exynos5_clock::div_acp, exynos5_clock::div_cdrex, exynos5_clock::div_core0, exynos5_clock::div_core1, exynos5_clock::div_cpu0, exynos5_clock::div_cpu1, exynos5_clock::div_fsys0, exynos5_clock::div_fsys2, exynos5_clock::div_isp0, exynos5_clock::div_isp1, exynos5_clock::div_isp2, exynos5_clock::div_lex, exynos5_clock::div_peric0, exynos5_clock::div_peric1, exynos5_clock::div_peric2, exynos5_clock::div_r0x, exynos5_clock::div_r1x, exynos5_clock::div_stat_acp, exynos5_clock::div_stat_cdrex, exynos5_clock::div_stat_core0, exynos5_clock::div_stat_core1, exynos5_clock::div_stat_cpu0, exynos5_clock::div_stat_cpu1, exynos5_clock::div_stat_fsys0, exynos5_clock::div_stat_lex, exynos5_clock::div_stat_r0x, exynos5_clock::div_stat_r1x, exynos5_clock::div_stat_syslft, exynos5_clock::div_stat_sysrgt, exynos5_clock::div_stat_top0, exynos5_clock::div_stat_top1, exynos5_clock::div_syslft, exynos5_clock::div_sysrgt, exynos5_clock::div_top0, exynos5_clock::div_top1, exynos5_clock::epll_con0, EPLL_CON0_LOCKED, exynos5_clock::epll_con1, EPLL_CON1_VAL, exynos5_clock::epll_con2, EPLL_CON2_VAL, exynos5_clock::epll_lock, EPLL_LOCK_VAL, mem_timings::epll_mdiv, mem_timings::epll_pdiv, mem_timings::epll_sdiv, exynos_clock, exynos_mct, exynos5_mct::g_tcon, exynos5_clock::gpll_con0, GPLL_CON0_LOCKED, exynos5_clock::gpll_con1, GPLL_CON1_VAL, exynos5_clock::gpll_lock, GPLL_LOCK_VAL, mem_timings::gpll_mdiv, mem_timings::gpll_pdiv, mem_timings::gpll_sdiv, HPM_SEL_SCLK_MPLL, MMC2_PRE_RATIO_OFFSET, MMC2_PRE_RATIO_VAL, MMC2_RATIO_OFFSET, MMC2_RATIO_VAL, MMC3_PRE_RATIO_OFFSET, MMC3_PRE_RATIO_VAL, MMC3_RATIO_OFFSET, MMC3_RATIO_VAL, exynos5_clock::mpll_con0, MPLL_CON0_LOCKED, exynos5_clock::mpll_con1, MPLL_CON1_VAL, exynos5_clock::mpll_lock, MPLL_LOCK_VAL, mem_timings::mpll_mdiv, mem_timings::mpll_pdiv, mem_timings::mpll_sdiv, MUX_APLL_SEL_MASK, MUX_BPLL_FOUT_SEL, MUX_BPLL_SEL_MASK, MUX_CPLL_SEL_MASK, MUX_EPLL_SEL_MASK, MUX_GPLL_SEL_MASK, MUX_HPM_SEL_MASK, MUX_MCLK_CDREX_SEL, MUX_MCLK_DPHY_SEL, MUX_MPLL_FOUT_SEL, MUX_MPLL_SEL_MASK, exynos5_clock::mux_stat_cdrex, exynos5_clock::mux_stat_core1, exynos5_clock::mux_stat_cpu, exynos5_clock::mux_stat_lex, exynos5_clock::mux_stat_top2, MUX_VPLL_SEL_MASK, arm_clk_ratios::pclk_dbg_ratio, arm_clk_ratios::periph_ratio, exynos5_clock::pll_div2_sel, read32(), exynos5_clock::sclk_div_isp, SCLK_DIV_ISP_VAL, exynos5_clock::sclk_src_isp, SCLK_SRC_ISP_VAL, set_pll, setbits32, exynos5_clock::src_cdrex, exynos5_clock::src_core0, exynos5_clock::src_core1, exynos5_clock::src_cpu, exynos5_clock::src_disp1_0, exynos5_clock::src_fsys, exynos5_clock::src_lex, exynos5_clock::src_peric0, exynos5_clock::src_peric1, exynos5_clock::src_top0, exynos5_clock::src_top1, exynos5_clock::src_top2, exynos5_clock::src_top3, TOP2_VAL, mem_timings::use_bpll, val, exynos5_clock::vpll_con0, VPLL_CON0_LOCKED, exynos5_clock::vpll_con1, VPLL_CON1_VAL, exynos5_clock::vpll_con2, VPLL_CON2_VAL, exynos5_clock::vpll_lock, VPLL_LOCK_VAL, mem_timings::vpll_mdiv, mem_timings::vpll_pdiv, mem_timings::vpll_sdiv, and write32().

Referenced by main(), and setup_clock().

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