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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <console/console.h>
#include <device/device.h>
#include <delay.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <intelblocks/power_limit.h>
#include <intelblocks/systemagent.h>
#include <soc/iomap.h>
#include <soc/soc_chip.h>
#include <soc/systemagent.h>
Go to the source code of this file.
Functions | |
void | soc_add_fixed_mmio_resources (struct device *dev, int *index) |
void | soc_systemagent_init (struct device *dev) |
uint32_t | soc_systemagent_max_chan_capacity_mib (u8 capid0_a_ddrsz) |
Definition at line 27 of file systemagent.c.
References ARRAY_SIZE, CAPID0_A, DMI_BASE_ADDRESS, DMI_BASE_SIZE, DMIBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, EDRAMBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, EPBAR, sa_mmio_descriptor::index, MCH_BASE_ADDRESS, MCH_BASE_SIZE, MCHBAR, pci_read_config32(), PCIEXBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, REGBAR, sa_add_fixed_mmio_resources(), soc_vtd_resources, and VTD_DISABLE.
Definition at line 55 of file systemagent.c.
References BIOS_ERR, config, config_of_soc, enable_bios_reset_cpl(), enable_power_aware_intr(), mdelay(), MOBILE_SKU_PL1_TIME_SEC, PCI_DEVICE_ID, PCI_DID_INTEL_TGL_ID_H_6_1, PCI_DID_INTEL_TGL_ID_H_8_1, PCI_DID_INTEL_TGL_ID_U_2_2, PCI_DID_INTEL_TGL_ID_U_4_2, PCI_DID_INTEL_TGL_ID_Y_2_2, PCI_DID_INTEL_TGL_ID_Y_4_2, pci_read_config16(), pcidev_path_on_root(), POWER_LIMITS_H_6_CORE, POWER_LIMITS_H_8_CORE, POWER_LIMITS_U_2_CORE, POWER_LIMITS_U_4_CORE, POWER_LIMITS_Y_2_CORE, POWER_LIMITS_Y_4_CORE, printk, SA_DEVFN_ROOT, and set_power_limits().
Definition at line 108 of file systemagent.c.