coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
systemagent_early.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #define __SIMPLE_DEVICE__
4 
5 #include <assert.h>
6 #include <device/mmio.h>
7 #include <device/pci_ops.h>
8 #include <device/device.h>
9 #include <device/pci.h>
13 #include <soc/iomap.h>
14 #include <soc/pci_devs.h>
15 #include <soc/systemagent.h>
16 
17 #include "systemagent_def.h"
18 
20 {
21  uint32_t reg;
22  uint8_t pciexbar_length;
23 
24  /*
25  * The PCIEXBAR is assumed to live in the memory mapped IO space under
26  * 4GiB.
27  */
28  reg = 0;
30 
31  /* Get PCI Express Region Length */
32  switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
33  case 256:
34  pciexbar_length = PCIEXBAR_LENGTH_256MB;
35  break;
36  case 128:
37  pciexbar_length = PCIEXBAR_LENGTH_128MB;
38  break;
39  case 64:
40  pciexbar_length = PCIEXBAR_LENGTH_64MB;
41  break;
42  default:
43  dead_code();
44  }
45  reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | (pciexbar_length << 1)
48 
49  /*
50  * TSEG defines the base of SMM range. BIOS determines the base
51  * of TSEG memory which must be at or below Graphics base of GTT
52  * Stolen memory, hence its better to clear TSEG register early
53  * to avoid power on default non-zero value (if any).
54  */
56 }
57 
58 void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources,
59  size_t count)
60 {
61  int i;
62 
63  for (i = 0; i < count; i++) {
64  uint64_t base;
65  unsigned int index;
66 
67  index = fixed_set_resources[i].index;
68  /* Check if PCI BAR already enabled */
70 
71  /* If enabled don't program it. */
73  return;
74 
75  base = fixed_set_resources[i].base;
76  if (base >> 32)
77  pci_write_config32(SA_DEV_ROOT, index + 4, base >> 32);
79  (base & 0xffffffff) | PCIEXBAR_PCIEXBAREN);
80  }
81 }
82 
83 /*
84  * There are special BARs that actually are programmed in the MCHBAR. These
85  * Intel special features, but they do consume resources that need to be
86  * accounted for.
87  */
88 void sa_set_mch_bar(const struct sa_mmio_descriptor *fixed_set_resources,
89  size_t count)
90 {
91  int i;
92 
93  for (i = 0; i < count; i++) {
94  uint64_t base;
95  unsigned int index;
96 
97  base = fixed_set_resources[i].base;
98  index = fixed_set_resources[i].index;
99  if (base >> 32)
100  write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index + 4), base >> 32);
101  write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index),
102  (base & 0xffffffff) | PCIEXBAR_PCIEXBAREN);
103  }
104 }
105 
107 {
108  /* All read and writes in this region are serviced by DRAM */
116 }
117 
119 {
120  u8 bios_reset_cpl;
121 
122  /*
123  * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
124  * that BIOS has initialized memory and power management
125  */
126  bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
127  bios_reset_cpl |= 3;
128  MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
129 }
130 
132 {
133  /* All regions concerned for have 1 MiB alignment. */
135 }
136 
138 {
139  /* All regions concerned for have 1 MiB alignment. */
141 }
142 
144 {
145  /* All regions concerned for have 1 MiB alignment. */
147 }
148 
149 size_t sa_get_tseg_size(void)
150 {
151  return sa_get_gsm_base() - sa_get_tseg_base();
152 }
153 
155 {
156  return (union dpr_register) { .raw = pci_read_config32(SA_DEV_ROOT, DPR) };
157 }
static void write32(void *addr, uint32_t val)
Definition: mmio.h:40
#define dead_code()
Definition: assert.h:89
#define ALIGN_DOWN(x, a)
Definition: helpers.h:18
#define MiB
Definition: helpers.h:76
#define MCHBAR8(x)
Definition: systemagent.h:21
#define PAM0
Definition: host_bridge.h:38
#define PAM6
Definition: host_bridge.h:44
#define PAM5
Definition: host_bridge.h:43
#define TOLUD
Definition: host_bridge.h:61
#define PCIEXBAR
Definition: host_bridge.h:32
#define PAM2
Definition: host_bridge.h:40
#define TSEG
Definition: host_bridge.h:60
#define PAM1
Definition: host_bridge.h:39
#define DPR
Definition: host_bridge.h:27
#define PAM3
Definition: host_bridge.h:41
#define BGSM
Definition: host_bridge.h:59
#define PAM4
Definition: host_bridge.h:42
#define BIOS_RESET_CPL
Definition: mchbar.h:62
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
Definition: pci_ops.h:76
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
Definition: pci_ops.h:58
static __always_inline void pci_write_config8(const struct device *dev, u16 reg, u8 val)
Definition: pci_ops.h:64
#define MCH_BASE_ADDRESS
Definition: iomap.h:82
static __always_inline void pci_io_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
Definition: pci_io_cfg.h:65
uintptr_t base
Definition: uart.c:17
#define SA_DEV_ROOT
Definition: pci_devs.h:26
unsigned int uint32_t
Definition: stdint.h:14
unsigned long uintptr_t
Definition: stdint.h:21
unsigned long long uint64_t
Definition: stdint.h:17
uint8_t u8
Definition: stdint.h:45
unsigned char uint8_t
Definition: stdint.h:8
unsigned int index
Definition: systemagent.h:45
#define PCIEXBAR_LENGTH_128MB
#define PCIEXBAR_LENGTH_64MB
#define PCIEXBAR_LENGTH_256MB
#define PCIEXBAR_PCIEXBAREN
void enable_bios_reset_cpl(void)
void sa_set_mch_bar(const struct sa_mmio_descriptor *fixed_set_resources, size_t count)
void enable_pam_region(void)
uintptr_t sa_get_tseg_base(void)
size_t sa_get_tseg_size(void)
union dpr_register txt_get_chipset_dpr(void)
uintptr_t sa_get_tolud_base(void)
uintptr_t sa_get_gsm_base(void)
void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources, size_t count)
void bootblock_systemagent_early_init(void)
uint32_t raw
Definition: txt_register.h:174
#define count
typedef void(X86APIP X86EMU_intrFuncs)(int num)