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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Macros | |
#define | DEFAULT_TBAR ((u8 *)0xfed1b000) |
#define | DEFAULT_PMBASE 0x00000500 /* Speedstep code has this hardcoded, too. */ |
#define | DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) |
#define | DEFAULT_GPIOBASE 0x00000580 |
#define | APM_CNT 0xb2 |
#define | GP_IO_USE_SEL 0x00 |
#define | GP_IO_SEL 0x04 |
#define | GP_LVL 0x0c |
#define | GPO_BLINK 0x18 |
#define | GPI_INV 0x2c |
#define | GP_IO_USE_SEL2 0x30 |
#define | GP_IO_SEL2 0x34 |
#define | GP_LVL2 0x38 |
#define | DEBUG_PERIODIC_SMIS 0 |
#define | MAINBOARD_POWER_OFF 0 |
#define | MAINBOARD_POWER_ON 1 |
#define | MAINBOARD_POWER_KEEP 2 |
#define | D31F0_ACPI_CNTL 0x44 |
#define | D31F0_GPIO_BASE 0x48 |
#define | D31F0_GPIO_CNTL 0x4c |
#define | D31F0_PIRQA_ROUT 0x60 |
#define | D31F0_PIRQB_ROUT 0x61 |
#define | D31F0_PIRQC_ROUT 0x62 |
#define | D31F0_PIRQD_ROUT 0x63 |
#define | D31F0_SERIRQ_CNTL 0x64 |
#define | D31F0_PIRQE_ROUT 0x68 |
#define | D31F0_PIRQF_ROUT 0x69 |
#define | D31F0_PIRQG_ROUT 0x6a |
#define | D31F0_PIRQH_ROUT 0x6b |
#define | D31F0_LPC_IODEC 0x80 |
#define | D31F0_LPC_EN 0x82 |
#define | CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ |
#define | CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ |
#define | MC_LPC_EN (1 << 11) /* 0x62/0x66 */ |
#define | KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ |
#define | GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ |
#define | GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ |
#define | FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ |
#define | LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ |
#define | COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ |
#define | COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ |
#define | D31F0_GEN1_DEC 0x84 |
#define | D31F0_GEN2_DEC 0x88 |
#define | D31F0_GEN3_DEC 0x8c |
#define | D31F0_GEN4_DEC 0x90 |
#define | D31F0_C5_EXIT_TIMING 0xa8 |
#define | D31F0_CxSTATE_CNF 0xa9 |
#define | D31F0_C4TIMING_CNT 0xaa |
#define | D31F2_IDE_TIM_PRI 0x40 |
#define | D31F2_IDE_TIM_SEC 0x42 |
#define | D31F2_SIDX 0xa0 |
#define | D31F2_SDAT 0xa4 |
#define | D30F0_SMLT 0x1b |
#define | D28Fx_XCAP 0x42 |
#define | D28Fx_SLCAP 0x54 |
#define | SMB_BASE 0x20 |
#define | HOSTC 0x40 |
#define | I2C_EN (1 << 2) |
#define | SMB_SMI_EN (1 << 1) |
#define | HST_EN (1 << 0) |
#define | RCBA_V0CTL 0x0014 |
#define | RCBA_V1CAP 0x001c |
#define | RCBA_V1CTL 0x0020 |
#define | RCBA_V1STS 0x0026 |
#define | RCBA_PAT 0x0030 |
#define | RCBA_CIR1 0x0088 |
#define | RCBA_ESD 0x0104 |
#define | RCBA_ULD 0x0110 |
#define | RCBA_ULBA 0x0118 |
#define | RCBA_LCAP 0x01a4 |
#define | RCBA_LCTL 0x01a8 |
#define | RCBA_LSTS 0x01aa |
#define | RCBA_CIR2 0x01f4 |
#define | RCBA_CIR3 0x01fc |
#define | RCBA_BCR 0x0220 |
#define | RCBA_DMIC 0x0234 |
#define | RCBA_RPFN 0x0238 |
#define | RCBA_CIR13 0x0f20 |
#define | RCBA_CIR5 0x1d40 |
#define | RCBA_DMC 0x2010 |
#define | RCBA_CIR6 0x2024 |
#define | RCBA_CIR7 0x2034 |
#define | RCBA_HPTC 0x3404 |
#define | GCS 0x3410 |
#define | RCBA_BUC 0x3414 |
#define | RCBA_FD 0x3418 /* Function Disable, see below. */ |
#define | RCBA_CG 0x341c |
#define | RCBA_FDSW 0x3420 |
#define | RCBA_CIR8 0x3430 |
#define | RCBA_CIR9 0x350c |
#define | RCBA_CIR10 0x352c |
#define | RCBA_MAP 0x35f0 /* UHCI controller #6 remapping */ |
#define | BUC_LAND (1 << 5) /* LAN */ |
#define | FD_SAD2 (1 << 25) /* SATA #2 */ |
#define | FD_TTD (1 << 24) /* Thermal Throttle */ |
#define | FD_PE6D (1 << 21) /* PCIe root port 6 */ |
#define | FD_PE5D (1 << 20) /* PCIe root port 5 */ |
#define | FD_PE4D (1 << 19) /* PCIe root port 4 */ |
#define | FD_PE3D (1 << 18) /* PCIe root port 3 */ |
#define | FD_PE2D (1 << 17) /* PCIe root port 2 */ |
#define | FD_PE1D (1 << 16) /* PCIe root port 1 */ |
#define | FD_EHCI1D (1 << 15) /* EHCI #1 */ |
#define | FD_LBD (1 << 14) /* LPC bridge */ |
#define | FD_EHCI2D (1 << 13) /* EHCI #2 */ |
#define | FD_U5D (1 << 12) /* UHCI #5 */ |
#define | FD_U4D (1 << 11) /* UHCI #4 */ |
#define | FD_U3D (1 << 10) /* UHCI #3 */ |
#define | FD_U2D (1 << 9) /* UHCI #2 */ |
#define | FD_U1D (1 << 8) /* UHCI #1 */ |
#define | FD_U6D (1 << 7) /* UHCI #6 */ |
#define | FD_HDAD (1 << 4) /* HD audio */ |
#define | FD_SD (1 << 3) /* SMBus */ |
#define | FD_SAD1 (1 << 2) /* SATA #1 */ |
#define | LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) |
Functions | |
static int | lpc_is_mobile (const u16 devid) |
void | aseg_smm_lock (void) |
void | i82801ix_early_init (void) |
void | i82801ix_lpc_setup (void) |
void | i82801ix_dmi_setup (void) |
void | i82801ix_dmi_poll_vc1 (void) |
#define APM_CNT 0xb2 |
Definition at line 23 of file i82801ix.h.
#define BUC_LAND (1 << 5) /* LAN */ |
Definition at line 128 of file i82801ix.h.
#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ |
Definition at line 56 of file i82801ix.h.
#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ |
Definition at line 55 of file i82801ix.h.
#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ |
Definition at line 64 of file i82801ix.h.
#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ |
Definition at line 63 of file i82801ix.h.
#define D28Fx_SLCAP 0x54 |
Definition at line 84 of file i82801ix.h.
#define D28Fx_XCAP 0x42 |
Definition at line 83 of file i82801ix.h.
#define D30F0_SMLT 0x1b |
Definition at line 80 of file i82801ix.h.
#define D31F0_ACPI_CNTL 0x44 |
Definition at line 41 of file i82801ix.h.
#define D31F0_C4TIMING_CNT 0xaa |
Definition at line 71 of file i82801ix.h.
#define D31F0_C5_EXIT_TIMING 0xa8 |
Definition at line 69 of file i82801ix.h.
#define D31F0_CxSTATE_CNF 0xa9 |
Definition at line 70 of file i82801ix.h.
#define D31F0_GEN1_DEC 0x84 |
Definition at line 65 of file i82801ix.h.
#define D31F0_GEN2_DEC 0x88 |
Definition at line 66 of file i82801ix.h.
#define D31F0_GEN3_DEC 0x8c |
Definition at line 67 of file i82801ix.h.
#define D31F0_GEN4_DEC 0x90 |
Definition at line 68 of file i82801ix.h.
#define D31F0_GPIO_BASE 0x48 |
Definition at line 42 of file i82801ix.h.
#define D31F0_GPIO_CNTL 0x4c |
Definition at line 43 of file i82801ix.h.
#define D31F0_LPC_EN 0x82 |
Definition at line 54 of file i82801ix.h.
#define D31F0_LPC_IODEC 0x80 |
Definition at line 53 of file i82801ix.h.
#define D31F0_PIRQA_ROUT 0x60 |
Definition at line 44 of file i82801ix.h.
#define D31F0_PIRQB_ROUT 0x61 |
Definition at line 45 of file i82801ix.h.
#define D31F0_PIRQC_ROUT 0x62 |
Definition at line 46 of file i82801ix.h.
#define D31F0_PIRQD_ROUT 0x63 |
Definition at line 47 of file i82801ix.h.
#define D31F0_PIRQE_ROUT 0x68 |
Definition at line 49 of file i82801ix.h.
#define D31F0_PIRQF_ROUT 0x69 |
Definition at line 50 of file i82801ix.h.
#define D31F0_PIRQG_ROUT 0x6a |
Definition at line 51 of file i82801ix.h.
#define D31F0_PIRQH_ROUT 0x6b |
Definition at line 52 of file i82801ix.h.
#define D31F0_SERIRQ_CNTL 0x64 |
Definition at line 48 of file i82801ix.h.
#define D31F2_IDE_TIM_PRI 0x40 |
Definition at line 74 of file i82801ix.h.
#define D31F2_IDE_TIM_SEC 0x42 |
Definition at line 75 of file i82801ix.h.
#define D31F2_SDAT 0xa4 |
Definition at line 77 of file i82801ix.h.
#define D31F2_SIDX 0xa0 |
Definition at line 76 of file i82801ix.h.
#define DEBUG_PERIODIC_SMIS 0 |
Definition at line 34 of file i82801ix.h.
#define DEFAULT_GPIOBASE 0x00000580 |
Definition at line 21 of file i82801ix.h.
#define DEFAULT_PMBASE 0x00000500 /* Speedstep code has this hardcoded, too. */ |
Definition at line 18 of file i82801ix.h.
#define DEFAULT_TBAR ((u8 *)0xfed1b000) |
Definition at line 6 of file i82801ix.h.
#define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) |
Definition at line 20 of file i82801ix.h.
#define FD_EHCI1D (1 << 15) /* EHCI #1 */ |
Definition at line 137 of file i82801ix.h.
#define FD_EHCI2D (1 << 13) /* EHCI #2 */ |
Definition at line 139 of file i82801ix.h.
#define FD_HDAD (1 << 4) /* HD audio */ |
Definition at line 146 of file i82801ix.h.
Definition at line 138 of file i82801ix.h.
#define FD_PE1D (1 << 16) /* PCIe root port 1 */ |
Definition at line 136 of file i82801ix.h.
#define FD_PE2D (1 << 17) /* PCIe root port 2 */ |
Definition at line 135 of file i82801ix.h.
#define FD_PE3D (1 << 18) /* PCIe root port 3 */ |
Definition at line 134 of file i82801ix.h.
#define FD_PE4D (1 << 19) /* PCIe root port 4 */ |
Definition at line 133 of file i82801ix.h.
#define FD_PE5D (1 << 20) /* PCIe root port 5 */ |
Definition at line 132 of file i82801ix.h.
#define FD_PE6D (1 << 21) /* PCIe root port 6 */ |
Definition at line 131 of file i82801ix.h.
#define FD_SAD1 (1 << 2) /* SATA #1 */ |
Definition at line 148 of file i82801ix.h.
#define FD_SAD2 (1 << 25) /* SATA #2 */ |
Definition at line 129 of file i82801ix.h.
#define FD_SD (1 << 3) /* SMBus */ |
Definition at line 147 of file i82801ix.h.
#define FD_TTD (1 << 24) /* Thermal Throttle */ |
Definition at line 130 of file i82801ix.h.
#define FD_U1D (1 << 8) /* UHCI #1 */ |
Definition at line 144 of file i82801ix.h.
#define FD_U2D (1 << 9) /* UHCI #2 */ |
Definition at line 143 of file i82801ix.h.
#define FD_U3D (1 << 10) /* UHCI #3 */ |
Definition at line 142 of file i82801ix.h.
#define FD_U4D (1 << 11) /* UHCI #4 */ |
Definition at line 141 of file i82801ix.h.
#define FD_U5D (1 << 12) /* UHCI #5 */ |
Definition at line 140 of file i82801ix.h.
#define FD_U6D (1 << 7) /* UHCI #6 */ |
Definition at line 145 of file i82801ix.h.
#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ |
Definition at line 61 of file i82801ix.h.
#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ |
Definition at line 59 of file i82801ix.h.
#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ |
Definition at line 60 of file i82801ix.h.
#define GCS 0x3410 |
Definition at line 118 of file i82801ix.h.
#define GP_IO_SEL 0x04 |
Definition at line 26 of file i82801ix.h.
#define GP_IO_SEL2 0x34 |
Definition at line 31 of file i82801ix.h.
#define GP_IO_USE_SEL 0x00 |
Definition at line 25 of file i82801ix.h.
#define GP_IO_USE_SEL2 0x30 |
Definition at line 30 of file i82801ix.h.
#define GP_LVL 0x0c |
Definition at line 27 of file i82801ix.h.
#define GP_LVL2 0x38 |
Definition at line 32 of file i82801ix.h.
#define GPI_INV 0x2c |
Definition at line 29 of file i82801ix.h.
#define GPO_BLINK 0x18 |
Definition at line 28 of file i82801ix.h.
#define HOSTC 0x40 |
Definition at line 88 of file i82801ix.h.
#define HST_EN (1 << 0) |
Definition at line 93 of file i82801ix.h.
#define I2C_EN (1 << 2) |
Definition at line 91 of file i82801ix.h.
#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ |
Definition at line 58 of file i82801ix.h.
#define LPC_IS_MOBILE | ( | dev | ) | lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) |
Definition at line 159 of file i82801ix.h.
#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ |
Definition at line 62 of file i82801ix.h.
#define MAINBOARD_POWER_KEEP 2 |
Definition at line 38 of file i82801ix.h.
#define MAINBOARD_POWER_OFF 0 |
Definition at line 36 of file i82801ix.h.
#define MAINBOARD_POWER_ON 1 |
Definition at line 37 of file i82801ix.h.
#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ |
Definition at line 57 of file i82801ix.h.
#define RCBA_BCR 0x0220 |
Definition at line 109 of file i82801ix.h.
#define RCBA_BUC 0x3414 |
Definition at line 119 of file i82801ix.h.
#define RCBA_CG 0x341c |
Definition at line 121 of file i82801ix.h.
#define RCBA_CIR1 0x0088 |
Definition at line 100 of file i82801ix.h.
#define RCBA_CIR10 0x352c |
Definition at line 125 of file i82801ix.h.
#define RCBA_CIR13 0x0f20 |
Definition at line 112 of file i82801ix.h.
#define RCBA_CIR2 0x01f4 |
Definition at line 107 of file i82801ix.h.
#define RCBA_CIR3 0x01fc |
Definition at line 108 of file i82801ix.h.
#define RCBA_CIR5 0x1d40 |
Definition at line 113 of file i82801ix.h.
#define RCBA_CIR6 0x2024 |
Definition at line 115 of file i82801ix.h.
#define RCBA_CIR7 0x2034 |
Definition at line 116 of file i82801ix.h.
#define RCBA_CIR8 0x3430 |
Definition at line 123 of file i82801ix.h.
#define RCBA_CIR9 0x350c |
Definition at line 124 of file i82801ix.h.
#define RCBA_DMC 0x2010 |
Definition at line 114 of file i82801ix.h.
#define RCBA_DMIC 0x0234 |
Definition at line 110 of file i82801ix.h.
#define RCBA_ESD 0x0104 |
Definition at line 101 of file i82801ix.h.
#define RCBA_FD 0x3418 /* Function Disable, see below. */ |
Definition at line 120 of file i82801ix.h.
#define RCBA_FDSW 0x3420 |
Definition at line 122 of file i82801ix.h.
#define RCBA_HPTC 0x3404 |
Definition at line 117 of file i82801ix.h.
#define RCBA_LCAP 0x01a4 |
Definition at line 104 of file i82801ix.h.
#define RCBA_LCTL 0x01a8 |
Definition at line 105 of file i82801ix.h.
#define RCBA_LSTS 0x01aa |
Definition at line 106 of file i82801ix.h.
#define RCBA_MAP 0x35f0 /* UHCI controller #6 remapping */ |
Definition at line 126 of file i82801ix.h.
#define RCBA_PAT 0x0030 |
Definition at line 99 of file i82801ix.h.
#define RCBA_RPFN 0x0238 |
Definition at line 111 of file i82801ix.h.
#define RCBA_ULBA 0x0118 |
Definition at line 103 of file i82801ix.h.
#define RCBA_ULD 0x0110 |
Definition at line 102 of file i82801ix.h.
#define RCBA_V0CTL 0x0014 |
Definition at line 95 of file i82801ix.h.
#define RCBA_V1CAP 0x001c |
Definition at line 96 of file i82801ix.h.
#define RCBA_V1CTL 0x0020 |
Definition at line 97 of file i82801ix.h.
#define RCBA_V1STS 0x0026 |
Definition at line 98 of file i82801ix.h.
#define SMB_BASE 0x20 |
Definition at line 87 of file i82801ix.h.
#define SMB_SMI_EN (1 << 1) |
Definition at line 92 of file i82801ix.h.
Definition at line 315 of file smi.c.
References BIOS_DEBUG, C_BASE_SEG, D_LCK, G_SMRAME, pci_write_config8(), pcidev_on_root(), printk, and SMRAM.
Definition at line 95 of file dmi_setup.c.
References BIOS_DEBUG, printk, RCBA16, RCBA32, RCBA_LSTS, and RCBA_V1STS.
Referenced by mainboard_romstage_entry().
Definition at line 26 of file dmi_setup.c.
References LPC_IS_MOBILE, PCI_DEV, RCBA16, RCBA32, RCBA8, RCBA_BCR, RCBA_CIR1, RCBA_CIR2, RCBA_CIR3, RCBA_CIR6, RCBA_DMC, RCBA_ESD, RCBA_LCAP, RCBA_LCTL, RCBA_PAT, RCBA_ULBA, RCBA_ULD, RCBA_V0CTL, RCBA_V1CAP, RCBA_V1CTL, and vc1_pat.
Referenced by mainboard_romstage_entry().
Definition at line 46 of file early_init.c.
References D31F0_ACPI_CNTL, D31F0_GPIO_BASE, D31F0_GPIO_CNTL, D31F0_PMBASE, DEFAULT_GPIOBASE, DEFAULT_PMBASE, DEFAULT_TCOBASE, enable_smbus(), ENV_ROMSTAGE, outw(), PCI_DEV, pci_or_config8(), pci_read_config8(), pci_write_config32(), pci_write_config8(), RCBA, and RCBA32.
Referenced by bootblock_early_southbridge_init(), and mainboard_romstage_entry().
Definition at line 10 of file early_init.c.
References device::chip_info, CNF1_LPC_EN, CNF2_LPC_EN, COMA_LPC_EN, COMB_LPC_EN, config, D31F0_GEN1_DEC, D31F0_GEN2_DEC, D31F0_GEN3_DEC, D31F0_GEN4_DEC, D31F0_LPC_EN, D31F0_LPC_IODEC, D31F0_SERIRQ_CNTL, FDD_LPC_EN, GAMEH_LPC_EN, GAMEL_LPC_EN, KBC_LPC_EN, LPT_LPC_EN, MC_LPC_EN, PCI_DEV, pci_write_config16(), pci_write_config32(), pci_write_config8(), and pcidev_on_root().
Referenced by bootblock_early_southbridge_init().
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inlinestatic |
Definition at line 155 of file i82801ix.h.