coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_init.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <bootblock_common.h>
4 #include <device/dram/ddr3.h>
9 
10 #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
11 
13  { 1, 0, 0 },
14  { 1, 0, 0 },
15  { 1, 0, 1 },
16  { 1, 0, 1 },
17  { 1, 0, 2 },
18  { 1, 0, 2 },
19  { 1, 0, 3 },
20  { 1, 0, 3 },
21  { 1, 0, 4 },
22  { 1, 0, 4 },
23  { 1, 0, 5 },
24  { 1, 0, 5 },
25  { 1, 0, 6 },
26  { 1, 0, 6 },
27 };
28 
30 {
31  nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
32 }
33 
34 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
35 {
36  read_spd(&spd[0], 0x50, id_only);
37  read_spd(&spd[2], 0x52, id_only);
38 }
Utilities for decoding DDR3 SPDs.
u8 spd_raw_data[256]
Definition: ddr3.h:156
void bootblock_mainboard_early_init(void)
Definition: early_init.c:11
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
Definition: early_init.c:25
const struct southbridge_usb_port mainboard_usb_ports[]
Definition: early_init.c:8
#define SERIAL_DEV
Definition: early_init.c:10
void read_spd(spd_raw_data *spd, u8 addr, bool id_only)
Definition: raminit.c:138
void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase)
Definition: early_serial.c:48