coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_init.c
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <
bootblock_common.h
>
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#include <
device/dram/ddr3.h
>
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#include <
northbridge/intel/sandybridge/raminit_native.h
>
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#include <
southbridge/intel/bd82x6x/pch.h
>
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#include <
superio/nuvoton/common/nuvoton.h
>
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#include <
superio/nuvoton/nct6776/nct6776.h
>
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#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
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const
struct
southbridge_usb_port
mainboard_usb_ports
[] = {
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{ 1, 0, 0 },
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{ 1, 0, 0 },
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{ 1, 0, 1 },
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{ 1, 0, 1 },
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{ 1, 0, 2 },
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{ 1, 0, 2 },
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{ 1, 0, 3 },
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{ 1, 0, 3 },
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{ 1, 0, 4 },
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{ 1, 0, 4 },
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{ 1, 0, 5 },
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{ 1, 0, 5 },
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{ 1, 0, 6 },
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{ 1, 0, 6 },
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};
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void
bootblock_mainboard_early_init
(
void
)
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{
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nuvoton_enable_serial
(
SERIAL_DEV
, CONFIG_TTYS0_BASE);
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}
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void
mainboard_get_spd
(
spd_raw_data
*spd,
bool
id_only)
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{
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read_spd
(&spd[0], 0x50, id_only);
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read_spd
(&spd[2], 0x52, id_only);
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}
bootblock_common.h
ddr3.h
Utilities for decoding DDR3 SPDs.
spd_raw_data
u8 spd_raw_data[256]
Definition:
ddr3.h:156
bootblock_mainboard_early_init
void bootblock_mainboard_early_init(void)
Definition:
early_init.c:11
mainboard_get_spd
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
Definition:
early_init.c:25
mainboard_usb_ports
const struct southbridge_usb_port mainboard_usb_ports[]
Definition:
early_init.c:8
SERIAL_DEV
#define SERIAL_DEV
Definition:
early_init.c:10
nct6776.h
read_spd
void read_spd(spd_raw_data *spd, u8 addr, bool id_only)
Definition:
raminit.c:138
nuvoton_enable_serial
void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase)
Definition:
early_serial.c:48
nuvoton.h
raminit_native.h
pch.h
southbridge_usb_port
Definition:
pch.h:56
src
mainboard
asus
h61-series
variants
p8h61-m_lx
early_init.c
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