coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
csme_ie_kt.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/pci.h>
4 #include <device/pci_ids.h>
5 #include <console/console.h>
6 #include <soc/pci_devs.h>
7 #include <soc/ramstage.h>
8 
9 /**
10 * Read the base address registers for a given device.
11 *
12 * @param dev Pointer to the dev structure.
13 * @param howmany How many registers to read.
14 */
15 static void pci_read_bases(struct device *dev, unsigned int howmany)
16 {
17  unsigned long index;
18 
19  for (index = PCI_BASE_ADDRESS_0;
20  (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) {
21  struct resource *resource;
23  /**
24  * Workaround for Denverton-NS silicon (Rev A0/A1 for CSME/IE,
25  * Rev B0 for CSME only)
26  * CSME&IEs KT IO bar must be 16-byte aligned
27  */
28  if ((resource->flags & IORESOURCE_IO) &&
29  (resource->align != 4)) {
31  "CSME&IEs KT IO bar must be 16-byte aligned!\n");
32  resource->align = 4;
33  resource->gran = 4;
34  resource->size = 16;
35  }
36  index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4;
37  }
38 
39  compact_resources(dev);
40 }
41 
42 static void pci_csme_ie_kt_read_resources(struct device *dev)
43 {
44  /**
45  * CSME/IE KT has 2 BARs to check:
46  * 0x10 - KT IO BAR
47  * 0x14 - KT Memory BAR
48  * CSME/IE KT has no Expansion ROM BAR to check:
49  * 0x30 - KT Host XRBAR, READ ONLY
50  */
51  pci_read_bases(dev, 2);
52 }
53 
54 static struct device_operations csme_ie_kt_ops = {
56  .set_resources = pci_dev_set_resources,
57  .enable_resources = pci_dev_enable_resources,
58  .ops_pci = &soc_pci_ops,
59 };
60 
61 static const unsigned short pci_device_ids[] = {
64  0
65 };
66 
67 static const struct pci_driver csme_ie_kt __pci_driver = {
68  .ops = &csme_ie_kt_ops,
69  .vendor = PCI_VID_INTEL,
70  .devices = pci_device_ids,
71 };
#define printk(level,...)
Definition: stdlib.h:16
static void pci_csme_ie_kt_read_resources(struct device *dev)
Definition: csme_ie_kt.c:42
static const struct pci_driver csme_ie_kt __pci_driver
Definition: csme_ie_kt.c:67
static void pci_read_bases(struct device *dev, unsigned int howmany)
Read the base address registers for a given device.
Definition: csme_ie_kt.c:15
static const unsigned short pci_device_ids[]
Definition: csme_ie_kt.c:61
static struct device_operations csme_ie_kt_ops
Definition: csme_ie_kt.c:54
void compact_resources(struct device *dev)
See if we have unused but allocated resource structures.
Definition: device_util.c:302
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
#define PCI_BASE_ADDRESS_0
Definition: pci_def.h:63
void pci_dev_enable_resources(struct device *dev)
Definition: pci_device.c:721
struct resource * pci_get_resource(struct device *dev, unsigned long index)
Given a device and register, read the size of the BAR for that register.
Definition: pci_device.c:86
void pci_dev_set_resources(struct device *dev)
Definition: pci_device.c:691
#define PCI_DID_INTEL_DNV_IE_KT
Definition: pci_ids.h:2784
#define PCI_DID_INTEL_DNV_ME_KT
Definition: pci_ids.h:2779
#define PCI_VID_INTEL
Definition: pci_ids.h:2157
#define IORESOURCE_PCI64
Definition: resource.h:39
#define IORESOURCE_IO
Definition: resource.h:9
struct pci_operations soc_pci_ops
Definition: chip.c:51
void(* read_resources)(struct device *dev)
Definition: device.h:39
Definition: device.h:107
unsigned long flags
Definition: resource.h:49
unsigned char align
Definition: resource.h:51
unsigned char gran
Definition: resource.h:52
unsigned long index
Definition: resource.h:50
resource_t size
Definition: resource.h:46