coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_init.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
bootblock_common.h
>
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#include <
device/pci_ops.h
>
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#include <
device/pnp_ops.h
>
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#include <
device/pnp_def.h
>
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#include <
option.h
>
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#include <
northbridge/intel/i945/i945.h
>
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#include <
southbridge/intel/i82801gx/i82801gx.h
>
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#include <
superio/winbond/common/winbond.h
>
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#include <
superio/winbond/w83627thg/w83627thg.h
>
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/* Override the default lpc decode ranges */
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void
mainboard_lpc_decode
(
void
)
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{
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int
lpt_en = 0;
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if
(
get_uint_option
(
"lpt"
, 0))
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lpt_en =
LPT_LPC_EN
;
/* enable LPT */
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pci_update_config16
(
PCI_DEV
(0, 0x1f, 0),
LPC_EN
, ~
LPT_LPC_EN
, lpt_en);
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}
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/* This box has two superios, so enabling serial becomes slightly excessive.
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* We disable a lot of stuff to make sure that there are no conflicts between
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* the two. Also set up the GPIOs from the beginning. This is the "no schematic
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* but safe anyways" method.
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*/
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void
bootblock_mainboard_early_init
(
void
)
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{
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pnp_devfn_t
dev;
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dev =
PNP_DEV
(0x2e,
W83627THG_SP1
);
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pnp_enter_conf_state
(dev);
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pnp_write_config
(dev, 0x24, 0xc6);
/* PNPCSV */
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pnp_write_config
(dev, 0x29, 0x43);
/* GPIO settings */
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pnp_write_config
(dev, 0x2a, 0x40);
/* GPIO settings */
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dev =
PNP_DEV
(0x2e,
W83627THG_SP1
);
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pnp_set_logical_device
(dev);
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pnp_set_enable
(dev, 0);
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pnp_set_iobase
(dev,
PNP_IDX_IO0
, 0x3f8);
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pnp_set_irq
(dev,
PNP_IDX_IRQ0
, 4);
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pnp_set_enable
(dev, 1);
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dev =
PNP_DEV
(0x2e,
W83627THG_SP2
);
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pnp_set_logical_device
(dev);
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pnp_set_enable
(dev, 0);
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pnp_set_iobase
(dev,
PNP_IDX_IO0
, 0x2f8);
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pnp_set_irq
(dev,
PNP_IDX_IRQ0
, 3);
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pnp_set_enable
(dev, 1);
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dev =
PNP_DEV
(0x2e,
W83627THG_KBC
);
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pnp_set_logical_device
(dev);
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pnp_set_enable
(dev, 0);
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pnp_set_iobase
(dev,
PNP_IDX_IO0
, 0x60);
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pnp_set_iobase
(dev,
PNP_IDX_IO1
, 0x64);
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pnp_set_enable
(dev, 1);
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dev =
PNP_DEV
(0x2e,
W83627THG_GAME_MIDI_GPIO1
);
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pnp_set_logical_device
(dev);
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pnp_set_enable
(dev, 0);
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pnp_write_config
(dev,
PNP_IDX_MSC5
, 0xff);
/* invert all GPIOs */
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pnp_set_enable
(dev, 1);
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dev =
PNP_DEV
(0x2e,
W83627THG_GPIO2
);
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pnp_set_logical_device
(dev);
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pnp_set_enable
(dev, 1);
/* Just enable it */
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dev =
PNP_DEV
(0x2e,
W83627THG_GPIO3
);
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pnp_set_logical_device
(dev);
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pnp_set_enable
(dev, 0);
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pnp_write_config
(dev,
PNP_IDX_MSC0
, 0xfb);
/* GPIO bit 2 is output */
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pnp_write_config
(dev,
PNP_IDX_MSC1
, 0x00);
/* GPIO bit 2 is 0 */
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/* Enable GPIO3+4. pnp_set_enable is not sufficient */
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pnp_write_config
(dev,
PNP_IDX_EN
, 0x03);
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dev =
PNP_DEV
(0x2e,
W83627THG_FDC
);
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pnp_set_logical_device
(dev);
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pnp_set_enable
(dev, 0);
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dev =
PNP_DEV
(0x2e,
W83627THG_PP
);
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pnp_set_logical_device
(dev);
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pnp_set_enable
(dev, 0);
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/* Enable HWM */
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dev =
PNP_DEV
(0x2e,
W83627THG_HWM
);
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pnp_set_logical_device
(dev);
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pnp_set_enable
(dev, 0);
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pnp_set_iobase
(dev,
PNP_IDX_IO0
, 0xa00);
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pnp_set_enable
(dev, 1);
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pnp_exit_conf_state
(dev);
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dev =
PNP_DEV
(0x4e,
W83627THG_SP1
);
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pnp_enter_conf_state
(dev);
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pnp_set_logical_device
(dev);
/* Set COM3 to sane non-conflicting values */
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pnp_set_enable
(dev, 0);
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pnp_set_iobase
(dev,
PNP_IDX_IO0
, 0x3e8);
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pnp_set_irq
(dev,
PNP_IDX_IRQ0
, 11);
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pnp_set_enable
(dev, 1);
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dev =
PNP_DEV
(0x4e,
W83627THG_SP2
);
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pnp_set_logical_device
(dev);
/* Set COM4 to sane non-conflicting values */
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pnp_set_enable
(dev, 0);
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pnp_set_iobase
(dev,
PNP_IDX_IO0
, 0x2e8);
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pnp_set_irq
(dev,
PNP_IDX_IRQ0
, 10);
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pnp_set_enable
(dev, 1);
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dev =
PNP_DEV
(0x4e,
W83627THG_FDC
);
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pnp_set_logical_device
(dev);
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pnp_set_enable
(dev, 0);
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dev =
PNP_DEV
(0x4e,
W83627THG_PP
);
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pnp_set_logical_device
(dev);
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pnp_set_enable
(dev, 0);
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dev =
PNP_DEV
(0x4e,
W83627THG_KBC
);
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pnp_set_logical_device
(dev);
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pnp_set_enable
(dev, 0);
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pnp_set_iobase
(dev,
PNP_IDX_IO0
, 0x00);
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pnp_set_iobase
(dev,
PNP_IDX_IO1
, 0x00);
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pnp_exit_conf_state
(dev);
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}
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void
mainboard_late_rcba_config
(
void
)
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{
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/* Device 1f interrupt pin register */
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RCBA32
(
D31IP
) = 0x00042210;
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/* Device 1d interrupt pin register */
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RCBA32
(
D28IP
) = 0x00214321;
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/* dev irq route register */
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RCBA16
(
D31IR
) = 0x0132;
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RCBA16
(
D30IR
) = 0x3241;
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RCBA16
(
D29IR
) = 0x0237;
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RCBA16
(
D28IR
) = 0x3210;
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RCBA16
(
D27IR
) = 0x3210;
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/* Enable PCIe Root Port Clock Gate */
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}
bootblock_common.h
i82801gx.h
i945.h
pci_ops.h
pci_update_config16
static __always_inline void pci_update_config16(const struct device *dev, u16 reg, u16 mask, u16 or)
Definition:
pci_ops.h:104
bootblock_mainboard_early_init
void bootblock_mainboard_early_init(void)
Definition:
early_init.c:11
mainboard_late_rcba_config
void mainboard_late_rcba_config(void)
Definition:
early_init.c:6
mainboard_lpc_decode
void mainboard_lpc_decode(void)
Definition:
early_init.c:34
get_uint_option
unsigned int get_uint_option(const char *name, const unsigned int fallback)
Definition:
option.c:116
option.h
PCI_DEV
#define PCI_DEV(SEGBUS, DEV, FN)
Definition:
pci_type.h:14
pnp_def.h
PNP_IDX_MSC0
#define PNP_IDX_MSC0
Definition:
pnp_def.h:14
PNP_IDX_MSC5
#define PNP_IDX_MSC5
Definition:
pnp_def.h:19
PNP_IDX_EN
#define PNP_IDX_EN
Definition:
pnp_def.h:4
PNP_IDX_MSC1
#define PNP_IDX_MSC1
Definition:
pnp_def.h:15
PNP_IDX_IO0
#define PNP_IDX_IO0
Definition:
pnp_def.h:5
PNP_IDX_IO1
#define PNP_IDX_IO1
Definition:
pnp_def.h:6
PNP_IDX_IRQ0
#define PNP_IDX_IRQ0
Definition:
pnp_def.h:10
pnp_set_irq
void pnp_set_irq(struct device *dev, u8 index, u8 irq)
Definition:
pnp_device.c:100
pnp_set_logical_device
void pnp_set_logical_device(struct device *dev)
Definition:
pnp_device.c:59
pnp_set_enable
void pnp_set_enable(struct device *dev, int enable)
Definition:
pnp_device.c:64
pnp_set_iobase
void pnp_set_iobase(struct device *dev, u8 index, u16 iobase)
Definition:
pnp_device.c:93
pnp_write_config
void pnp_write_config(struct device *dev, u8 reg, u8 value)
Definition:
pnp_device.c:38
pnp_ops.h
PNP_DEV
#define PNP_DEV(PORT, FUNC)
Definition:
pnp_type.h:10
pnp_devfn_t
u32 pnp_devfn_t
Definition:
pnp_type.h:8
LPT_LPC_EN
#define LPT_LPC_EN
Definition:
lpc.h:44
LPC_EN
#define LPC_EN
Definition:
lpc.h:36
D31IR
#define D31IR
Definition:
rcba.h:87
D30IR
#define D30IR
Definition:
rcba.h:88
D28IR
#define D28IR
Definition:
rcba.h:90
D31IP
#define D31IP
Definition:
rcba.h:56
D29IR
#define D29IR
Definition:
rcba.h:89
D27IR
#define D27IR
Definition:
rcba.h:91
D28IP
#define D28IP
Definition:
rcba.h:65
RCBA16
#define RCBA16(x)
Definition:
rcba.h:13
RCBA32
#define RCBA32(x)
Definition:
rcba.h:14
pnp_exit_conf_state
void pnp_exit_conf_state(pnp_devfn_t dev)
Definition:
early_init.c:40
pnp_enter_conf_state
void pnp_enter_conf_state(pnp_devfn_t dev)
Definition:
early_init.c:32
w83627thg.h
W83627THG_GPIO2
#define W83627THG_GPIO2
Definition:
w83627thg.h:14
W83627THG_KBC
#define W83627THG_KBC
Definition:
w83627thg.h:12
W83627THG_GPIO3
#define W83627THG_GPIO3
Definition:
w83627thg.h:15
W83627THG_SP1
#define W83627THG_SP1
Definition:
w83627thg.h:10
W83627THG_GAME_MIDI_GPIO1
#define W83627THG_GAME_MIDI_GPIO1
Definition:
w83627thg.h:13
W83627THG_HWM
#define W83627THG_HWM
Definition:
w83627thg.h:17
W83627THG_SP2
#define W83627THG_SP2
Definition:
w83627thg.h:11
W83627THG_PP
#define W83627THG_PP
Definition:
w83627thg.h:9
W83627THG_FDC
#define W83627THG_FDC
Definition:
w83627thg.h:8
winbond.h
src
mainboard
kontron
986lcd-m
early_init.c
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