coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
qcom_qup_se.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <soc/qcom_qup_se.h>
4 
5 struct qup qup[12] = {
6  [0] = { .regs = (void *)QUP_SERIAL0_BASE,
7  .pin = { GPIO(34), GPIO(35), GPIO(36), GPIO(37) },
8  .func = { GPIO34_FUNC_QUP0_L0, GPIO35_FUNC_QUP0_L1,
9  GPIO36_FUNC_QUP0_L2, GPIO37_FUNC_QUP0_L3 }
10  },
11  [1] = { .regs = (void *)QUP_SERIAL1_BASE,
12  .pin = { GPIO(0), GPIO(1), GPIO(2), GPIO(3),
13  GPIO(12), GPIO(94) },
14  .func = { GPIO0_FUNC_QUP0_L0, GPIO1_FUNC_QUP0_L1,
15  GPIO2_FUNC_QUP0_L2, GPIO3_FUNC_QUP0_L3,
16  GPIO12_FUNC_QUP0_L4, GPIO94_FUNC_QUP0_L5 }
17  },
18  [2] = { .regs = (void *)QUP_SERIAL2_BASE,
19  .pin = { GPIO(15), GPIO(16) },
20  .func = { GPIO15_FUNC_QUP0_L0, GPIO16_FUNC_QUP0_L1 }
21  },
22  [3] = { .regs = (void *)QUP_SERIAL3_BASE,
23  .pin = { GPIO(38), GPIO(39), GPIO(40), GPIO(41) },
24  .func = { GPIO38_FUNC_QUP0_L0, GPIO39_FUNC_QUP0_L1,
25  GPIO40_FUNC_QUP0_L2, GPIO41_FUNC_QUP0_L3 }
26  },
27  [4] = { .regs = (void *)QUP_SERIAL4_BASE,
28  .pin = { GPIO(115), GPIO(116) },
29  .func = { GPIO115_FUNC_QUP0_L0, GPIO116_FUNC_QUP0_L1 }
30  },
31  [5] = { .regs = (void *)QUP_SERIAL5_BASE,
32  .pin = { GPIO(25), GPIO(26), GPIO(27), GPIO(28) },
33  .func = { GPIO25_FUNC_QUP0_L0, GPIO26_FUNC_QUP0_L1,
34  GPIO27_FUNC_QUP0_L2, GPIO28_FUNC_QUP0_L3 }
35  },
36  [6] = { .regs = (void *)QUP_SERIAL6_BASE,
37  .pin = { GPIO(59), GPIO(60), GPIO(61), GPIO(62),
38  GPIO(68), GPIO(72) },
39  .func = { GPIO59_FUNC_QUP1_L0, GPIO60_FUNC_QUP1_L1,
40  GPIO61_FUNC_QUP1_L2, GPIO62_FUNC_QUP1_L3,
41  GPIO68_FUNC_QUP1_L4, GPIO72_FUNC_QUP1_L5 }
42  },
43  [7] = { .regs = (void *)QUP_SERIAL7_BASE,
44  .pin = { GPIO(6), GPIO(7) },
45  .func = { GPIO6_FUNC_QUP1_L0, GPIO7_FUNC_QUP1_L1 }
46  },
47  [8] = { .regs = (void *)QUP_SERIAL8_BASE,
48  .pin = { GPIO(42), GPIO(43), GPIO(44), GPIO(45) },
49  .func = { GPIO42_FUNC_QUP1_L0, GPIO43_FUNC_QUP1_L1,
50  GPIO44_FUNC_QUP1_L2, GPIO45_FUNC_QUP1_L3 }
51  },
52  [9] = { .regs = (void *)QUP_SERIAL9_BASE,
53  .pin = { GPIO(46), GPIO(47) },
54  .func = { GPIO46_FUNC_QUP1_L0, GPIO47_FUNC_QUP1_L1 }
55  },
56  [10] = { .regs = (void *)QUP_SERIAL10_BASE,
57  .pin = { GPIO(86), GPIO(87), GPIO(88), GPIO(89),
58  GPIO(90), GPIO(91) },
59  .func = { GPIO86_FUNC_QUP1_L0, GPIO87_FUNC_QUP1_L1,
60  GPIO88_FUNC_QUP1_L2, GPIO89_FUNC_QUP1_L3,
61  GPIO90_FUNC_QUP1_L4, GPIO91_FUNC_QUP1_L5 }
62  },
63  [11] = { .regs = (void *)QUP_SERIAL11_BASE,
64  .pin = { GPIO(53), GPIO(54), GPIO(55), GPIO(56) },
65  .func = { GPIO53_FUNC_QUP1_L0, GPIO54_FUNC_QUP1_L1,
66  GPIO55_FUNC_QUP1_L2, GPIO56_FUNC_QUP1_L3 }
67  },
68 };
@ GPIO
Definition: chip.h:84
#define QUP_SERIAL0_BASE
Definition: addressmap.h:20
#define QUP_SERIAL1_BASE
Definition: addressmap.h:21
#define QUP_SERIAL5_BASE
Definition: addressmap.h:25
#define QUP_SERIAL9_BASE
Definition: addressmap.h:32
#define QUP_SERIAL7_BASE
Definition: addressmap.h:30
#define QUP_SERIAL2_BASE
Definition: addressmap.h:22
#define QUP_SERIAL3_BASE
Definition: addressmap.h:23
#define QUP_SERIAL4_BASE
Definition: addressmap.h:24
#define QUP_SERIAL8_BASE
Definition: addressmap.h:31
#define QUP_SERIAL10_BASE
Definition: addressmap.h:33
#define QUP_SERIAL11_BASE
Definition: addressmap.h:34
#define QUP_SERIAL6_BASE
Definition: addressmap.h:29
struct qup_regs * regs
Definition: qcom_qup_se.h:29
gpio_t pin[6]
Definition: qcom_qup_se.h:30