coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
dpm_4ch.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <console/console.h>
4 #include <delay.h>
5 #include <device/mmio.h>
6 #include <soc/dpm.h>
7 #include <soc/dramc_soc.h>
8 #include <soc/spm.h>
9 #include <soc/symbols.h>
10 
11 static struct dpm_regs *const mtk_dpm2 = (void *)DPM_CFG_BASE2;
12 
13 static int wake_dpm_sram_up(void)
14 {
15  int loop = 100;
16 
17  /* TODO: convert to new APIs (SET32_BITFIELDS/READ32_BITFIELD) */
20 
21  while (loop > 0 &&
26  mdelay(1);
27  --loop;
28  }
29 
30  if (loop == 0) {
31  printk(BIOS_ERR, "failed to wake DPM up.\n");
32  return -1;
33  }
34 
37 
38  return 0;
39 }
40 
41 static void dpm_mtcoms_sleep_on(void)
42 {
43  /* DPM MTCMOS sleep on */
44  write32(&mtk_spm->dpm0_pwr_con, 0x0000204d);
45  write32(&mtk_spm->dpm1_pwr_con, 0x0000204d);
46  mdelay(1);
47  write32(&mtk_spm->dpm0_pwr_con, 0x0000224d);
48  write32(&mtk_spm->dpm1_pwr_con, 0x0000224d);
49  mdelay(1);
52 }
53 
54 static struct mtk_mcu dpm_mcu_4ch[] = {
55  {
56  .firmware_name = CONFIG_DPM_DM_FIRMWARE,
57  .run_address = (void *)DPM_DM_SRAM_BASE2,
58  },
59  {
60  .firmware_name = CONFIG_DPM_PM_FIRMWARE,
61  .run_address = (void *)DPM_PM_SRAM_BASE2,
62  .priv = mtk_dpm2,
63  .reset = dpm_reset,
64  },
65 };
66 
67 int dpm_4ch_init(void)
68 {
70  if (wake_dpm_sram_up())
71  return -1;
72  return 0;
73 }
74 
76 {
77  int i;
78  struct mtk_mcu *dpm;
79 
80  for (i = 0; i < ARRAY_SIZE(dpm_mcu_4ch); i++) {
81  dpm = &dpm_mcu_4ch[i];
82  dpm->load_buffer = _dram_dma;
83  dpm->buffer_size = REGION_SIZE(dram_dma);
84  if (mtk_init_mcu(dpm))
85  return -1;
86  }
87 
88  return 0;
89 }
static void write32(void *addr, uint32_t val)
Definition: mmio.h:40
static uint32_t read32(const void *addr)
Definition: mmio.h:22
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define printk(level,...)
Definition: stdlib.h:16
void mdelay(unsigned int msecs)
Definition: delay.c:2
void dpm_reset(struct mtk_mcu *mcu)
Definition: dpm.c:21
#define DRAMC_MCU_SRAM_ISOINT_B_LSB
Definition: dpm.h:44
static struct dpm_regs *const mtk_dpm
Definition: dpm.h:49
#define DRAMC_MCU2_SRAM_ISOINT_B_LSB
Definition: dpm.h:45
#define DRAMC_MCU2_SRAM_SLEEP_B_LSB
Definition: dpm.h:47
#define DRAMC_MCU_SRAM_SLEEP_B_LSB
Definition: dpm.h:46
#define DPM_SW_RSTN_RESET
Definition: dpm.h:40
static struct mtk_mcu dpm_mcu_4ch[]
Definition: dpm_4ch.c:54
static void dpm_mtcoms_sleep_on(void)
Definition: dpm_4ch.c:41
static struct dpm_regs *const mtk_dpm2
Definition: dpm_4ch.c:11
int dpm_4ch_para_setting(void)
Definition: dpm_4ch.c:75
int dpm_4ch_init(void)
Definition: dpm_4ch.c:67
static int wake_dpm_sram_up(void)
Definition: dpm_4ch.c:13
#define setbits32(addr, set)
Definition: mmio.h:21
#define clrbits32(addr, clear)
Definition: mmio.h:26
#define REGION_SIZE(name)
Definition: symbols.h:10
#define BIOS_ERR
BIOS_ERR - System in incomplete state.
Definition: loglevel.h:72
int mtk_init_mcu(struct mtk_mcu *mcu)
Definition: mcu.c:10
static struct mtk_spm_regs *const mtk_spm
Definition: spm.h:154
@ DPM_PM_SRAM_BASE2
Definition: addressmap.h:56
@ DPM_CFG_BASE2
Definition: addressmap.h:58
@ DPM_DM_SRAM_BASE2
Definition: addressmap.h:57
Definition: dpm.h:10
u32 sw_rstn
Definition: dpm.h:11
size_t buffer_size
Definition: mcu_common.h:11
const char * firmware_name
Definition: mcu_common.h:7
void * priv
Definition: mcu_common.h:12
void * load_buffer
Definition: mcu_common.h:10
uint32_t dramc_mcu2_sram_con
Definition: spm.h:343
u32 dpm0_pwr_con
Definition: spm.h:594
uint32_t dramc_mcu_sram_con
Definition: spm.h:344
u32 dpm1_pwr_con
Definition: spm.h:595
static void __noreturn reset(void)