coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
uart.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <amdblocks/aoac.h>
4 #include <amdblocks/gpio.h>
5 #include <amdblocks/uart.h>
6 #include <commonlib/helpers.h>
7 #include <console/console.h>
8 #include <device/device.h>
9 #include <device/mmio.h>
10 #include <soc/aoac_defs.h>
11 #include <soc/gpio.h>
12 #include <soc/southbridge.h>
13 #include <soc/uart.h>
14 #include <types.h>
15 
16 static const struct {
18  struct soc_amd_gpio mux[2];
19 } uart_info[] = {
20  [0] = { APU_UART0_BASE, {
21  PAD_NF(GPIO_143, UART0_TXD, PULL_NONE),
22  PAD_NF(GPIO_141, UART0_RXD, PULL_NONE),
23  } },
24  [1] = { APU_UART1_BASE, {
25  PAD_NF(GPIO_140, UART1_TXD, PULL_NONE),
26  PAD_NF(GPIO_142, UART1_RXD, PULL_NONE),
27  } },
28  [2] = { APU_UART2_BASE, {
29  PAD_NF(GPIO_138, UART2_TXD, PULL_NONE),
30  PAD_NF(GPIO_136, UART2_RXD, PULL_NONE),
31  } },
32  [3] = { APU_UART3_BASE, {
33  PAD_NF(GPIO_135, UART3_TXD, PULL_NONE),
34  PAD_NF(GPIO_137, UART3_RXD, PULL_NONE),
35  } },
36  [4] = { APU_UART4_BASE, {
37  PAD_NF(GPIO_156, UART4_TXD, PULL_NONE),
38  PAD_NF(GPIO_155, UART4_RXD, PULL_NONE),
39  } },
40 };
41 
42 uintptr_t get_uart_base(unsigned int idx)
43 {
44  if (idx >= ARRAY_SIZE(uart_info))
45  return 0;
46 
47  return uart_info[idx].base;
48 }
49 
51 {
52  write16((void *)FCH_LEGACY_UART_DECODE, 0);
53 }
54 
55 void set_uart_config(unsigned int idx)
56 {
57  if (idx >= ARRAY_SIZE(uart_info))
58  return;
59 
61 }
62 
63 static const char *uart_acpi_name(const struct device *dev)
64 {
65  switch (dev->path.mmio.addr) {
66  case APU_UART0_BASE:
67  return "FUR0";
68  case APU_UART1_BASE:
69  return "FUR1";
70  case APU_UART2_BASE:
71  return "FUR2";
72  case APU_UART3_BASE:
73  return "FUR3";
74  case APU_UART4_BASE:
75  return "FUR4";
76  default:
77  return NULL;
78  }
79 }
80 
81 /* Even though this is called enable, it gets called for both enabled and disabled devices. */
82 static void uart_enable(struct device *dev)
83 {
84  unsigned int dev_id;
85 
86  switch (dev->path.mmio.addr) {
87  case APU_UART0_BASE:
89  break;
90  case APU_UART1_BASE:
92  break;
93  case APU_UART2_BASE:
95  break;
96  case APU_UART3_BASE:
98  break;
99  case APU_UART4_BASE:
101  break;
102  default:
103  printk(BIOS_ERR, "%s: Unknown device: %s\n", __func__, dev_path(dev));
104  return;
105  }
106 
107  if (dev->enabled) {
110  } else {
112  }
113 }
114 
115 static void uart_read_resources(struct device *dev)
116 {
117  mmio_resource(dev, 0, dev->path.mmio.addr / KiB, 4);
118 }
119 
122  .set_resources = noop_set_resources,
123  .scan_bus = scan_static_bus,
124  .enable = uart_enable,
125  .acpi_name = uart_acpi_name,
126  .acpi_fill_ssdt = uart_inject_ssdt,
127 };
#define APU_UART0_BASE
Definition: iomap.h:19
#define APU_UART1_BASE
Definition: iomap.h:20
static void write16(void *addr, uint16_t val)
Definition: mmio.h:35
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define KiB
Definition: helpers.h:75
void wait_for_aoac_enabled(unsigned int dev)
Definition: aoac.c:35
#define FCH_AOAC_DEV_UART1
Definition: aoac_defs.h:15
#define FCH_AOAC_DEV_UART0
Definition: aoac_defs.h:14
#define FCH_LEGACY_UART_DECODE
Definition: southbridge.h:86
void power_off_aoac_device(unsigned int dev)
Definition: aoac.c:17
void power_on_aoac_device(unsigned int dev)
Definition: aoac.c:8
#define printk(level,...)
Definition: stdlib.h:16
const char * dev_path(const struct device *dev)
Definition: device_util.c:149
#define PULL_NONE
Definition: buildOpts.c:72
static void noop_set_resources(struct device *dev)
Definition: device.h:74
#define mmio_resource(dev, idx, basek, sizek)
Definition: device.h:334
#define BIOS_ERR
BIOS_ERR - System in incomplete state.
Definition: loglevel.h:72
u16 dev_id
#define FCH_AOAC_DEV_UART2
Definition: aoac_defs.h:13
#define FCH_AOAC_DEV_UART3
Definition: aoac_defs.h:15
void scan_static_bus(struct device *bus)
Definition: root_device.c:89
#define FCH_AOAC_DEV_UART4
Definition: aoac_defs.h:18
#define GPIO_143
Definition: gpio.h:90
#define GPIO_141
Definition: gpio.h:88
#define GPIO_140
Definition: gpio.h:87
#define GPIO_142
Definition: gpio.h:89
uintptr_t get_uart_base(unsigned int idx)
Definition: uart.c:9
void set_uart_config(unsigned int idx)
Definition: uart.c:43
uintptr_t base
Definition: uart.c:17
void clear_uart_legacy_config(void)
Definition: uart.c:38
void gpio_configure_pads(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
program a particular set of GPIO
Definition: gpio.c:307
#define PAD_NF(pin, func, pull)
Definition: gpio_defs.h:208
void uart_inject_ssdt(const struct device *dev)
Definition: uart_acpi.c:8
#define GPIO_136
Definition: gpio.h:91
#define GPIO_137
Definition: gpio.h:92
#define GPIO_138
Definition: gpio.h:93
#define GPIO_135
Definition: gpio.h:90
#define GPIO_156
Definition: gpio.h:106
#define GPIO_155
Definition: gpio.h:105
static const struct @427 uart_info[]
static void uart_enable(struct device *dev)
Definition: uart.c:82
static void uart_read_resources(struct device *dev)
Definition: uart.c:115
struct device_operations sabrina_uart_mmio_ops
Definition: uart.c:120
static const char * uart_acpi_name(const struct device *dev)
Definition: uart.c:63
#define NULL
Definition: stddef.h:19
unsigned long uintptr_t
Definition: stdint.h:21
void(* read_resources)(struct device *dev)
Definition: device.h:39
struct mmio_path mmio
Definition: path.h:128
Definition: device.h:107
struct device_path path
Definition: device.h:115
unsigned int enabled
Definition: device.h:122
uintptr_t addr
Definition: path.h:106
Definition: pll_common.h:22