#include <arch/cpu.h>
#include <stdint.h>

Include dependency graph for haswell.h:

This graph shows which files directly or indirectly include this file:

Macros
#define	HASWELL_FAMILY_TRAD 0x306c0

#define	HASWELL_FAMILY_ULT 0x40650

#define	CRYSTALWELL_FAMILY 0x306c0

#define	BROADWELL_FAMILY_ULT 0x306d0

#define	CPUID_HASWELL_A0 0x306c1

#define	CPUID_HASWELL_B0 0x306c2

#define	CPUID_HASWELL_C0 0x306c3

#define	CPUID_HASWELL_ULT_B0 0x40650

#define	CPUID_HASWELL_ULT_C0 0x40651

#define	CPUID_CRYSTALWELL_B0 0x40660

#define	CPUID_CRYSTALWELL_C0 0x40661

#define	CPUID_BROADWELL_C0 0x40671

#define	CPUID_BROADWELL_ULT_C0 0x306d2

#define	CPUID_BROADWELL_ULT_D0 0x306d3

#define	CPUID_BROADWELL_ULT_E0 0x306d4

#define	CPU_BCLK 100

#define	MSR_CORE_THREAD_COUNT 0x35

#define	MSR_PLATFORM_INFO 0xce

#define	PLATFORM_INFO_SET_TDP (1 << 29)

#define	TIMED_MWAIT_SUPPORTED (1 << (37 - 32))

#define	MSR_PKG_CST_CONFIG_CONTROL 0xe2

#define	MSR_PMG_IO_CAPTURE_BASE 0xe4

#define	MSR_FEATURE_CONFIG 0x13c

#define	SMM_MCA_CAP_MSR 0x17d

#define	SMM_CPU_SVRSTR_BIT 57

#define	SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))

#define	MSR_FLEX_RATIO 0x194

#define	FLEX_RATIO_LOCK (1 << 20)

#define	FLEX_RATIO_EN (1 << 16)

#define	MSR_TEMPERATURE_TARGET 0x1a2

#define	MSR_MISC_PWR_MGMT 0x1aa

#define	MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)

#define	MSR_TURBO_RATIO_LIMIT 0x1ad

#define	MSR_PRMRR_PHYS_BASE 0x1f4

#define	MSR_PRMRR_PHYS_MASK 0x1f5

#define	MSR_POWER_CTL 0x1fc

#define	MSR_LT_LOCK_MEMORY 0x2e7

#define	MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4

#define	MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5

#define	SMM_FEATURE_CONTROL_MSR 0x4e0

#define	SMM_CPU_SAVE_EN (1 << 1)

#define	MSR_C_STATE_LATENCY_CONTROL_0 0x60a

#define	MSR_C_STATE_LATENCY_CONTROL_1 0x60b

#define	MSR_C_STATE_LATENCY_CONTROL_2 0x60c

#define	MSR_C_STATE_LATENCY_CONTROL_3 0x633

#define	MSR_C_STATE_LATENCY_CONTROL_4 0x634

#define	MSR_C_STATE_LATENCY_CONTROL_5 0x635

#define	IRTL_VALID (1 << 15)

#define	IRTL_1_NS (0 << 10)

#define	IRTL_32_NS (1 << 10)

#define	IRTL_1024_NS (2 << 10)

#define	IRTL_32768_NS (3 << 10)

#define	IRTL_1048576_NS (4 << 10)

#define	IRTL_33554432_NS (5 << 10)

#define	IRTL_RESPONSE_MASK (0x3ff)

#define	MSR_PKG_POWER_LIMIT 0x610

#define	PKG_POWER_LIMIT_MASK 0x7fff

#define	PKG_POWER_LIMIT_EN (1 << 15)

#define	PKG_POWER_LIMIT_CLAMP (1 << 16)

#define	PKG_POWER_LIMIT_TIME_SHIFT 17

#define	PKG_POWER_LIMIT_TIME_MASK 0x7f

#define	MSR_VR_CURRENT_CONFIG 0x601

#define	MSR_VR_MISC_CONFIG 0x603

#define	MSR_PKG_POWER_SKU_UNIT 0x606

#define	MSR_PKG_POWER_SKU 0x614

#define	MSR_DDR_RAPL_LIMIT 0x618

#define	MSR_VR_MISC_CONFIG2 0x636

#define	MSR_PP0_POWER_LIMIT 0x638

#define	MSR_PP1_POWER_LIMIT 0x640

#define	MSR_CONFIG_TDP_NOMINAL 0x648

#define	MSR_CONFIG_TDP_LEVEL1 0x649

#define	MSR_CONFIG_TDP_LEVEL2 0x64a

#define	MSR_CONFIG_TDP_CONTROL 0x64b

#define	MSR_TURBO_ACTIVATION_RATIO 0x64c

#define	SMBASE_MSR 0xc20

#define	IEDBASE_MSR 0xc22

#define	SMRR_SUPPORTED (1 << 11)

#define	PRMRR_SUPPORTED (1 << 12)

#define	C_STATE_LATENCY_CONTROL_0_LIMIT 0x42

#define	C_STATE_LATENCY_CONTROL_1_LIMIT 0x73

#define	C_STATE_LATENCY_CONTROL_2_LIMIT 0x91

#define	C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4

#define	C_STATE_LATENCY_CONTROL_4_LIMIT 0x145

#define	C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef

#define	C_STATE_LATENCY_MICRO_SECONDS(limit, base) (((1 << ((base) * 5)) * (limit)) / 1000)

#define	C_STATE_LATENCY_FROM_LAT_REG(reg)

#define	PSS_MAX_ENTRIES 8

#define	PSS_RATIO_STEP 2

#define	PSS_LATENCY_TRANSITION 10

#define	PSS_LATENCY_BUSMASTER 10

Enumerations
enum	{ C_STATE_C0 = 0 , C_STATE_C1 = 1 , C_STATE_C1E = 2 , C_STATE_C3 = 3 , C_STATE_C6_SHORT_LAT = 4 , C_STATE_C6_LONG_LAT = 5 , C_STATE_C7_SHORT_LAT = 6 , C_STATE_C7_LONG_LAT = 7 , C_STATE_C7S_SHORT_LAT = 8 , C_STATE_C7S_LONG_LAT = 9 , C_STATE_C8 = 10 , C_STATE_C9 = 11 , C_STATE_C10 = 12 , NUM_C_STATES }

Functions
void	intel_cpu_haswell_finalize_smm (void)

void	set_power_limits (u8 power_limit_1_time)

int	cpu_config_tdp_levels (void)

void	set_max_freq (void)

static u32	cpu_family_model (void)

static u32	cpu_stepping (void)

static int	haswell_is_ult (void)

Macro Definition Documentation

◆ BROADWELL_FAMILY_ULT

#define BROADWELL_FAMILY_ULT 0x306d0

Definition at line 13 of file haswell.h.

◆ C_STATE_LATENCY_CONTROL_0_LIMIT

#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42

Definition at line 110 of file haswell.h.

◆ C_STATE_LATENCY_CONTROL_1_LIMIT

#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73

Definition at line 111 of file haswell.h.

◆ C_STATE_LATENCY_CONTROL_2_LIMIT

#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91

Definition at line 112 of file haswell.h.

◆ C_STATE_LATENCY_CONTROL_3_LIMIT

#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4

Definition at line 113 of file haswell.h.

◆ C_STATE_LATENCY_CONTROL_4_LIMIT

#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145

Definition at line 114 of file haswell.h.

◆ C_STATE_LATENCY_CONTROL_5_LIMIT

#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef

Definition at line 115 of file haswell.h.

◆ C_STATE_LATENCY_FROM_LAT_REG

#define C_STATE_LATENCY_FROM_LAT_REG ( reg )

Value:

C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \

(IRTL_1024_NS >> 10))

C_STATE_LATENCY_MICRO_SECONDS

#define C_STATE_LATENCY_MICRO_SECONDS(limit, base)

Definition: haswell.h:117

IRTL_1024_NS

#define IRTL_1024_NS

Definition: haswell.h:72

Definition at line 119 of file haswell.h.

◆ C_STATE_LATENCY_MICRO_SECONDS

#define C_STATE_LATENCY_MICRO_SECONDS	(	limit,
		base
	)	(((1 << ((base) * 5)) * (limit)) / 1000)

Definition at line 117 of file haswell.h.

◆ CPU_BCLK

#define CPU_BCLK 100

Definition at line 35 of file haswell.h.

◆ CPUID_BROADWELL_C0

#define CPUID_BROADWELL_C0 0x40671

Definition at line 28 of file haswell.h.

◆ CPUID_BROADWELL_ULT_C0

#define CPUID_BROADWELL_ULT_C0 0x306d2

Definition at line 30 of file haswell.h.

◆ CPUID_BROADWELL_ULT_D0

#define CPUID_BROADWELL_ULT_D0 0x306d3

Definition at line 31 of file haswell.h.

◆ CPUID_BROADWELL_ULT_E0

#define CPUID_BROADWELL_ULT_E0 0x306d4

Definition at line 32 of file haswell.h.

◆ CPUID_CRYSTALWELL_B0

#define CPUID_CRYSTALWELL_B0 0x40660

Definition at line 24 of file haswell.h.

◆ CPUID_CRYSTALWELL_C0

#define CPUID_CRYSTALWELL_C0 0x40661

Definition at line 25 of file haswell.h.

◆ CPUID_HASWELL_A0

#define CPUID_HASWELL_A0 0x306c1

Definition at line 16 of file haswell.h.

◆ CPUID_HASWELL_B0

#define CPUID_HASWELL_B0 0x306c2

Definition at line 17 of file haswell.h.

◆ CPUID_HASWELL_C0

#define CPUID_HASWELL_C0 0x306c3

Definition at line 18 of file haswell.h.

◆ CPUID_HASWELL_ULT_B0

#define CPUID_HASWELL_ULT_B0 0x40650

Definition at line 20 of file haswell.h.

◆ CPUID_HASWELL_ULT_C0

#define CPUID_HASWELL_ULT_C0 0x40651

Definition at line 21 of file haswell.h.

◆ CRYSTALWELL_FAMILY

#define CRYSTALWELL_FAMILY 0x306c0

Definition at line 12 of file haswell.h.

◆ FLEX_RATIO_EN

#define FLEX_RATIO_EN (1 << 16)

Definition at line 49 of file haswell.h.

◆ FLEX_RATIO_LOCK

#define FLEX_RATIO_LOCK (1 << 20)

Definition at line 48 of file haswell.h.

◆ HASWELL_FAMILY_TRAD

#define HASWELL_FAMILY_TRAD 0x306c0

Definition at line 10 of file haswell.h.

◆ HASWELL_FAMILY_ULT

#define HASWELL_FAMILY_ULT 0x40650

Definition at line 11 of file haswell.h.

◆ IEDBASE_MSR

#define IEDBASE_MSR 0xc22

Definition at line 103 of file haswell.h.

◆ IRTL_1024_NS

#define IRTL_1024_NS (2 << 10)

Definition at line 72 of file haswell.h.

◆ IRTL_1048576_NS

#define IRTL_1048576_NS (4 << 10)

Definition at line 74 of file haswell.h.

◆ IRTL_1_NS

#define IRTL_1_NS (0 << 10)

Definition at line 70 of file haswell.h.

◆ IRTL_32768_NS

#define IRTL_32768_NS (3 << 10)

Definition at line 73 of file haswell.h.

◆ IRTL_32_NS

#define IRTL_32_NS (1 << 10)

Definition at line 71 of file haswell.h.

◆ IRTL_33554432_NS

#define IRTL_33554432_NS (5 << 10)

Definition at line 75 of file haswell.h.

◆ IRTL_RESPONSE_MASK

#define IRTL_RESPONSE_MASK (0x3ff)

Definition at line 76 of file haswell.h.

◆ IRTL_VALID

#define IRTL_VALID (1 << 15)

Definition at line 69 of file haswell.h.

◆ MISC_PWR_MGMT_EIST_HW_DIS

#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)

Definition at line 52 of file haswell.h.

◆ MSR_C_STATE_LATENCY_CONTROL_0

#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a

Definition at line 63 of file haswell.h.

◆ MSR_C_STATE_LATENCY_CONTROL_1

#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b

Definition at line 64 of file haswell.h.

◆ MSR_C_STATE_LATENCY_CONTROL_2

#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c

Definition at line 65 of file haswell.h.

◆ MSR_C_STATE_LATENCY_CONTROL_3

#define MSR_C_STATE_LATENCY_CONTROL_3 0x633

Definition at line 66 of file haswell.h.

◆ MSR_C_STATE_LATENCY_CONTROL_4

#define MSR_C_STATE_LATENCY_CONTROL_4 0x634

Definition at line 67 of file haswell.h.

◆ MSR_C_STATE_LATENCY_CONTROL_5

#define MSR_C_STATE_LATENCY_CONTROL_5 0x635

Definition at line 68 of file haswell.h.

◆ MSR_CONFIG_TDP_CONTROL

#define MSR_CONFIG_TDP_CONTROL 0x64b

Definition at line 98 of file haswell.h.

◆ MSR_CONFIG_TDP_LEVEL1

#define MSR_CONFIG_TDP_LEVEL1 0x649

Definition at line 96 of file haswell.h.

◆ MSR_CONFIG_TDP_LEVEL2

#define MSR_CONFIG_TDP_LEVEL2 0x64a

Definition at line 97 of file haswell.h.

◆ MSR_CONFIG_TDP_NOMINAL

#define MSR_CONFIG_TDP_NOMINAL 0x648

Definition at line 95 of file haswell.h.

◆ MSR_CORE_THREAD_COUNT

#define MSR_CORE_THREAD_COUNT 0x35

Definition at line 37 of file haswell.h.

◆ MSR_DDR_RAPL_LIMIT

#define MSR_DDR_RAPL_LIMIT 0x618

Definition at line 90 of file haswell.h.

◆ MSR_FEATURE_CONFIG

#define MSR_FEATURE_CONFIG 0x13c

Definition at line 43 of file haswell.h.

◆ MSR_FLEX_RATIO

#define MSR_FLEX_RATIO 0x194

Definition at line 47 of file haswell.h.

◆ MSR_LT_LOCK_MEMORY

#define MSR_LT_LOCK_MEMORY 0x2e7

Definition at line 57 of file haswell.h.

◆ MSR_MISC_PWR_MGMT

#define MSR_MISC_PWR_MGMT 0x1aa

Definition at line 51 of file haswell.h.

◆ MSR_PKG_CST_CONFIG_CONTROL

#define MSR_PKG_CST_CONFIG_CONTROL 0xe2

Definition at line 41 of file haswell.h.

◆ MSR_PKG_POWER_LIMIT

#define MSR_PKG_POWER_LIMIT 0x610

Definition at line 79 of file haswell.h.

◆ MSR_PKG_POWER_SKU

#define MSR_PKG_POWER_SKU 0x614

Definition at line 89 of file haswell.h.

◆ MSR_PKG_POWER_SKU_UNIT

#define MSR_PKG_POWER_SKU_UNIT 0x606

Definition at line 88 of file haswell.h.

◆ MSR_PLATFORM_INFO

#define MSR_PLATFORM_INFO 0xce

Definition at line 38 of file haswell.h.

◆ MSR_PMG_IO_CAPTURE_BASE

#define MSR_PMG_IO_CAPTURE_BASE 0xe4

Definition at line 42 of file haswell.h.

◆ MSR_POWER_CTL

#define MSR_POWER_CTL 0x1fc

Definition at line 56 of file haswell.h.

◆ MSR_PP0_POWER_LIMIT

#define MSR_PP0_POWER_LIMIT 0x638

Definition at line 92 of file haswell.h.

◆ MSR_PP1_POWER_LIMIT

#define MSR_PP1_POWER_LIMIT 0x640

Definition at line 93 of file haswell.h.

◆ MSR_PRMRR_PHYS_BASE

#define MSR_PRMRR_PHYS_BASE 0x1f4

Definition at line 54 of file haswell.h.

◆ MSR_PRMRR_PHYS_MASK

#define MSR_PRMRR_PHYS_MASK 0x1f5

Definition at line 55 of file haswell.h.

◆ MSR_TEMPERATURE_TARGET

#define MSR_TEMPERATURE_TARGET 0x1a2

Definition at line 50 of file haswell.h.

◆ MSR_TURBO_ACTIVATION_RATIO

#define MSR_TURBO_ACTIVATION_RATIO 0x64c

Definition at line 99 of file haswell.h.

◆ MSR_TURBO_RATIO_LIMIT

#define MSR_TURBO_RATIO_LIMIT 0x1ad

Definition at line 53 of file haswell.h.

◆ MSR_UNCORE_PRMRR_PHYS_BASE

#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4

Definition at line 58 of file haswell.h.

◆ MSR_UNCORE_PRMRR_PHYS_MASK

#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5

Definition at line 59 of file haswell.h.

◆ MSR_VR_CURRENT_CONFIG

#define MSR_VR_CURRENT_CONFIG 0x601

Definition at line 86 of file haswell.h.

◆ MSR_VR_MISC_CONFIG

#define MSR_VR_MISC_CONFIG 0x603

Definition at line 87 of file haswell.h.

◆ MSR_VR_MISC_CONFIG2

#define MSR_VR_MISC_CONFIG2 0x636

Definition at line 91 of file haswell.h.

◆ PKG_POWER_LIMIT_CLAMP

#define PKG_POWER_LIMIT_CLAMP (1 << 16)

Definition at line 82 of file haswell.h.

◆ PKG_POWER_LIMIT_EN

#define PKG_POWER_LIMIT_EN (1 << 15)

Definition at line 81 of file haswell.h.

◆ PKG_POWER_LIMIT_MASK

#define PKG_POWER_LIMIT_MASK 0x7fff

Definition at line 80 of file haswell.h.

◆ PKG_POWER_LIMIT_TIME_MASK

#define PKG_POWER_LIMIT_TIME_MASK 0x7f

Definition at line 84 of file haswell.h.

◆ PKG_POWER_LIMIT_TIME_SHIFT

#define PKG_POWER_LIMIT_TIME_SHIFT 17

Definition at line 83 of file haswell.h.

◆ PLATFORM_INFO_SET_TDP

#define PLATFORM_INFO_SET_TDP (1 << 29)

Definition at line 39 of file haswell.h.

◆ PRMRR_SUPPORTED

#define PRMRR_SUPPORTED (1 << 12)

Definition at line 107 of file haswell.h.

◆ PSS_LATENCY_BUSMASTER

#define PSS_LATENCY_BUSMASTER 10

Definition at line 127 of file haswell.h.

◆ PSS_LATENCY_TRANSITION

#define PSS_LATENCY_TRANSITION 10

Definition at line 126 of file haswell.h.

◆ PSS_MAX_ENTRIES

#define PSS_MAX_ENTRIES 8

Definition at line 124 of file haswell.h.

◆ PSS_RATIO_STEP

#define PSS_RATIO_STEP 2

Definition at line 125 of file haswell.h.

◆ SMBASE_MSR

#define SMBASE_MSR 0xc20

Definition at line 102 of file haswell.h.

◆ SMM_CPU_SAVE_EN

#define SMM_CPU_SAVE_EN (1 << 1)

Definition at line 61 of file haswell.h.

◆ SMM_CPU_SVRSTR_BIT

#define SMM_CPU_SVRSTR_BIT 57

Definition at line 45 of file haswell.h.

◆ SMM_CPU_SVRSTR_MASK

#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))

Definition at line 46 of file haswell.h.

◆ SMM_FEATURE_CONTROL_MSR

#define SMM_FEATURE_CONTROL_MSR 0x4e0

Definition at line 60 of file haswell.h.

◆ SMM_MCA_CAP_MSR

#define SMM_MCA_CAP_MSR 0x17d

Definition at line 44 of file haswell.h.

◆ SMRR_SUPPORTED

#define SMRR_SUPPORTED (1 << 11)

Definition at line 106 of file haswell.h.

◆ TIMED_MWAIT_SUPPORTED

#define TIMED_MWAIT_SUPPORTED (1 << (37 - 32))

Definition at line 40 of file haswell.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Enumerator
C_STATE_C0
C_STATE_C1
C_STATE_C1E
C_STATE_C3
C_STATE_C6_SHORT_LAT
C_STATE_C6_LONG_LAT
C_STATE_C7_SHORT_LAT
C_STATE_C7_LONG_LAT
C_STATE_C7S_SHORT_LAT
C_STATE_C7S_LONG_LAT
C_STATE_C8
C_STATE_C9
C_STATE_C10
NUM_C_STATES

Definition at line 147 of file haswell.h.

Function Documentation

◆ cpu_config_tdp_levels()

int cpu_config_tdp_levels ( void )

Definition at line 300 of file haswell_init.c.

References msr_struct::hi, MSR_PLATFORM_INFO, and rdmsr().

Referenced by generate_P_state_entries(), northbridge_init(), set_max_turbo_freq(), set_power_limits(), and soc_power_states_generation().

Here is the call graph for this function:

Here is the caller graph for this function:

◆ cpu_family_model()

static u32 cpu_family_model ( void )

inlinestatic

Definition at line 174 of file haswell.h.

References cpuid_eax().

Here is the call graph for this function:

◆ cpu_stepping()

static u32 cpu_stepping ( void )

inlinestatic

Definition at line 179 of file haswell.h.

References cpuid_eax().

Here is the call graph for this function:

◆ haswell_is_ult()

static int haswell_is_ult ( void )

inlinestatic

Definition at line 184 of file haswell.h.

References CONFIG.

Referenced by configure_c_states(), generate_C_state_entries(), gma_pm_init_post_vbios(), initialize_vr_config(), is_s0ix_enabled(), and pre_mp_init().

Here is the caller graph for this function:

◆ intel_cpu_haswell_finalize_smm()

void intel_cpu_haswell_finalize_smm ( void )

Definition at line 8 of file finalize.c.

References BIT, MSR_LT_LOCK_MEMORY, and msr_set().

Referenced by southbridge_smi_apmc().

Here is the call graph for this function:

Here is the caller graph for this function:

◆ set_max_freq()

void set_max_freq ( void )

Definition at line 7 of file romstage.c.

References BIOS_DEBUG, CPU_BCLK, msr_struct::hi, IA32_PERF_CTL, msr_struct::lo, MSR_CONFIG_TDP_NOMINAL, MSR_PLATFORM_INFO, printk, rdmsr(), and wrmsr().

Referenced by bootblock_soc_init(), and soc_init_pre_device().

Here is the call graph for this function:

Here is the caller graph for this function:

◆ set_power_limits()

void set_power_limits ( u8 power_limit_1_time )

Definition at line 313 of file haswell_init.c.

References ARRAY_SIZE, BIOS_DEBUG, cpu_config_tdp_levels(), msr_struct::hi, msr_struct::lo, MCH_DDR_POWER_LIMIT_HI, MCH_DDR_POWER_LIMIT_LO, MCH_PKG_POWER_LIMIT_HI, MCH_PKG_POWER_LIMIT_LO, mchbar_read32(), mchbar_write32(), MSR_CONFIG_TDP_NOMINAL, MSR_DDR_RAPL_LIMIT, MSR_PKG_POWER_LIMIT, MSR_PKG_POWER_SKU, MSR_PKG_POWER_SKU_UNIT, MSR_PLATFORM_INFO, MSR_TURBO_ACTIVATION_RATIO, PKG_POWER_LIMIT_EN, PKG_POWER_LIMIT_MASK, PKG_POWER_LIMIT_TIME_MASK, PKG_POWER_LIMIT_TIME_SHIFT, PLATFORM_INFO_SET_TDP, power_limit_time_msr_to_sec, power_limit_time_sec_to_msr, printk, rdmsr(), and wrmsr().

Referenced by northbridge_init(), soc_init(), soc_systemagent_init(), and systemagent_init().

Here is the call graph for this function:

Here is the caller graph for this function:

Macros

Enumerations

Functions

Macro Definition Documentation

◆ BROADWELL_FAMILY_ULT

◆ C_STATE_LATENCY_CONTROL_0_LIMIT

◆ C_STATE_LATENCY_CONTROL_1_LIMIT

◆ C_STATE_LATENCY_CONTROL_2_LIMIT

◆ C_STATE_LATENCY_CONTROL_3_LIMIT

◆ C_STATE_LATENCY_CONTROL_4_LIMIT

◆ C_STATE_LATENCY_CONTROL_5_LIMIT

◆ C_STATE_LATENCY_FROM_LAT_REG

◆ C_STATE_LATENCY_MICRO_SECONDS

◆ CPU_BCLK

◆ CPUID_BROADWELL_C0

◆ CPUID_BROADWELL_ULT_C0

◆ CPUID_BROADWELL_ULT_D0

◆ CPUID_BROADWELL_ULT_E0

◆ CPUID_CRYSTALWELL_B0

◆ CPUID_CRYSTALWELL_C0

◆ CPUID_HASWELL_A0

◆ CPUID_HASWELL_B0

◆ CPUID_HASWELL_C0

◆ CPUID_HASWELL_ULT_B0

◆ CPUID_HASWELL_ULT_C0

◆ CRYSTALWELL_FAMILY

◆ FLEX_RATIO_EN

◆ FLEX_RATIO_LOCK

◆ HASWELL_FAMILY_TRAD

◆ HASWELL_FAMILY_ULT

◆ IEDBASE_MSR

◆ IRTL_1024_NS

◆ IRTL_1048576_NS

◆ IRTL_1_NS

◆ IRTL_32768_NS

◆ IRTL_32_NS

◆ IRTL_33554432_NS

◆ IRTL_RESPONSE_MASK

◆ IRTL_VALID

◆ MISC_PWR_MGMT_EIST_HW_DIS

◆ MSR_C_STATE_LATENCY_CONTROL_0

◆ MSR_C_STATE_LATENCY_CONTROL_1

◆ MSR_C_STATE_LATENCY_CONTROL_2

◆ MSR_C_STATE_LATENCY_CONTROL_3

◆ MSR_C_STATE_LATENCY_CONTROL_4

◆ MSR_C_STATE_LATENCY_CONTROL_5

◆ MSR_CONFIG_TDP_CONTROL

◆ MSR_CONFIG_TDP_LEVEL1

◆ MSR_CONFIG_TDP_LEVEL2

◆ MSR_CONFIG_TDP_NOMINAL

◆ MSR_CORE_THREAD_COUNT

◆ MSR_DDR_RAPL_LIMIT

◆ MSR_FEATURE_CONFIG

◆ MSR_FLEX_RATIO

◆ MSR_LT_LOCK_MEMORY

◆ MSR_MISC_PWR_MGMT

◆ MSR_PKG_CST_CONFIG_CONTROL

◆ MSR_PKG_POWER_LIMIT

◆ MSR_PKG_POWER_SKU

◆ MSR_PKG_POWER_SKU_UNIT

◆ MSR_PLATFORM_INFO

◆ MSR_PMG_IO_CAPTURE_BASE

◆ MSR_POWER_CTL

◆ MSR_PP0_POWER_LIMIT

◆ MSR_PP1_POWER_LIMIT

◆ MSR_PRMRR_PHYS_BASE

◆ MSR_PRMRR_PHYS_MASK

◆ MSR_TEMPERATURE_TARGET

◆ MSR_TURBO_ACTIVATION_RATIO

◆ MSR_TURBO_RATIO_LIMIT

◆ MSR_UNCORE_PRMRR_PHYS_BASE

◆ MSR_UNCORE_PRMRR_PHYS_MASK

◆ MSR_VR_CURRENT_CONFIG

◆ MSR_VR_MISC_CONFIG

◆ MSR_VR_MISC_CONFIG2

◆ PKG_POWER_LIMIT_CLAMP

◆ PKG_POWER_LIMIT_EN

◆ PKG_POWER_LIMIT_MASK

◆ PKG_POWER_LIMIT_TIME_MASK

◆ PKG_POWER_LIMIT_TIME_SHIFT