160 mask = ((1ULL << 20) - 1);
179 #define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \
182 .is_64_bit = is_64_, \
183 .is_limit = is_limit_, \
184 .description = desc_, \
187 #define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_)
188 #define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_)
189 #define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_)
240 unsigned long base_k, size_k, touud_k, index;
285 index = *resource_cnt;
289 size_k = (0xa0000 >> 10) - base_k;
293 base_k = 0xc0000 >> 10;
294 size_k = (
unsigned long)(mc_values[
TSEG_REG] >> 10) - base_k;
315 base_k = 4096 * 1024;
317 size_k = touud_k - base_k;
318 if (touud_k > base_k)
326 mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
329 *resource_cnt = index;
359 static const struct {
360 const unsigned int devfn;
362 const char *
const name;
386 deven &= ~nb_devs[i].mask;
411 const bool is_haswell_h = !
CONFIG(INTEL_LYNXPOINT_LP);
446 for (
unsigned int i = 0; i <= 2; i++) {
558 static const struct pci_driver mc_driver_hsw
__pci_driver = {
581 CHIP_NAME(
"Intel Haswell integrated Northbridge")
#define printk(level,...)
void generate_cpu_entries(const struct device *device)
void set_power_limits(u8 power_limit_1_time)
void mdelay(unsigned int msecs)
DEVTREE_CONST struct device * pcidev_path_on_root(pci_devfn_t devfn)
DEVTREE_CONST struct device * pcidev_on_root(uint8_t dev, uint8_t fn)
struct resource * new_resource(struct device *dev, unsigned int index)
See if a resource structure already exists for a given index and if not allocate one.
void mmconf_resource(struct device *dev, unsigned long index)
#define mchbar_setbits32(addr, set)
static __always_inline void mchbar_clrsetbits8(uintptr_t offset, uint8_t clear, uint8_t set)
static __always_inline void epbar_clrsetbits32(uintptr_t offset, uint32_t clear, uint32_t set)
static __always_inline void dmibar_write32(const uintptr_t offset, const uint32_t value)
#define mchbar_setbits8(addr, set)
#define dmibar_setbits32(addr, set)
static __always_inline uint32_t mchbar_read32(const uintptr_t offset)
static __always_inline uint16_t epbar_read16(const uintptr_t offset)
#define dmibar_setbits16(addr, set)
static __always_inline void dmibar_clrsetbits32(uintptr_t offset, uint32_t clear, uint32_t set)
static __always_inline void epbar_write32(const uintptr_t offset, const uint32_t value)
static void noop_read_resources(struct device *dev)
Standard device operations function pointers shims.
static void noop_set_resources(struct device *dev)
static void mp_cpu_bus_init(struct device *dev)
#define ram_resource(dev, idx, basek, sizek)
#define mmio_resource(dev, idx, basek, sizek)
#define reserved_ram_resource(dev, idx, basek, sizek)
static __always_inline void pci_or_config32(const struct device *dev, u16 reg, u32 ormask)
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
static __always_inline void pci_update_config32(const struct device *dev, u16 reg, u32 mask, u32 or)
static __always_inline void pci_or_config16(const struct device *dev, u16 reg, u16 ormask)
static __always_inline u16 pci_read_config16(const struct device *dev, u16 reg)
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start)
#define GFXVT_BASE_ADDRESS
#define VTVC0_BASE_ADDRESS
static struct map_entry memory_map[NUM_MAP_ENTRIES]
static struct device_operations cpu_bus_ops
static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len)
static void northbridge_topology_init(void)
#define MAP_ENTRY_LIMIT_64(reg_, desc_)
static struct device_operations pci_domain_ops
static struct device_operations mc_ops
static void mc_read_resources(struct device *dev)
static void enable_dev(struct device *dev)
static void mc_report_map_entries(struct device *dev, uint64_t *values)
static void mc_add_fixed_mmio_resources(struct device *dev)
#define MAP_ENTRY_BASE_64(reg_, desc_)
static void disable_devices(void)
static void mc_read_map_entries(struct device *dev, uint64_t *values)
static void northbridge_dmi_init(void)
#define MAP_ENTRY_BASE_32(reg_, desc_)
static void init_egress(void)
static void northbridge_final(struct device *dev)
static const struct pci_driver mc_driver_hsw __pci_driver
static const unsigned short mc_pci_device_ids[]
static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result)
struct fixed_mmio_descriptor mc_fixed_resources[]
static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
static const char * northbridge_acpi_name(const struct device *dev)
static void northbridge_init(struct device *dev)
struct chip_operations northbridge_intel_haswell_ops
static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
@ DEVICE_PATH_CPU_CLUSTER
#define PCI_DEVFN(slot, func)
void pci_domain_read_resources(struct device *dev)
void pci_dev_enable_resources(struct device *dev)
void pci_domain_set_resources(struct device *dev)
void pci_dev_read_resources(struct device *dev)
struct pci_operations pci_dev_ops_pci
Default device operation for PCI devices.
void pci_dev_set_resources(struct device *dev)
void pci_domain_scan_bus(struct device *dev)
Scan a PCI domain.
#define PCI_DEV(SEGBUS, DEV, FN)
#define IORESOURCE_RESERVE
#define IORESOURCE_CACHEABLE
#define IORESOURCE_STORED
#define IORESOURCE_ASSIGNED
unsigned long long uint64_t
void(* read_resources)(struct device *dev)
enum device_path_type type
struct device_operations * ops
DEVTREE_CONST struct bus * bus
int(* get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size)