coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <
console/console.h
>
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#include <
romstage_handoff.h
>
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#include <
southbridge/intel/common/pmclib.h
>
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#include <
arch/romstage.h
>
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#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)
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#include <
southbridge/intel/i82801jx/i82801jx.h
>
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#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
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#include <
southbridge/intel/i82801gx/i82801gx.h
>
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#endif
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#include "
raminit.h
"
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#include "
x4x.h
"
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__weak
void
mb_pre_raminit_setup
(
int
s3_resume)
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{
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}
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void
mainboard_romstage_entry
(
void
)
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{
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u8
spd_addr_map[4] = {};
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u8
boot_path = 0;
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u8
s3_resume;
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#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)
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i82801jx_early_init
();
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#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
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i82801gx_early_init
();
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#endif
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x4x_early_init
();
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s3_resume =
southbridge_detect_s3_resume
();
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mb_pre_raminit_setup
(s3_resume);
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if
(s3_resume)
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boot_path =
BOOT_PATH_RESUME
;
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if
(
mchbar_read32
(
PMSTS_MCHBAR
) &
PMSTS_WARM_RESET
)
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boot_path =
BOOT_PATH_WARM_RESET
;
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mb_get_spd_map
(spd_addr_map);
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sdram_initialize
(boot_path, spd_addr_map);
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x4x_late_init
();
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printk
(
BIOS_DEBUG
,
"x4x late init complete\n"
);
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romstage_handoff_init
(s3_resume);
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}
romstage.h
printk
#define printk(level,...)
Definition:
stdlib.h:16
console.h
mchbar_read32
static __always_inline uint32_t mchbar_read32(const uintptr_t offset)
Definition:
fixed_bars.h:21
PMSTS_WARM_RESET
#define PMSTS_WARM_RESET
Definition:
gm45.h:226
PMSTS_MCHBAR
#define PMSTS_MCHBAR
Definition:
gm45.h:225
i82801gx.h
i82801gx_early_init
void i82801gx_early_init(void)
i82801jx.h
BOOT_PATH_RESUME
#define BOOT_PATH_RESUME
Definition:
raminit.h:35
BIOS_DEBUG
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition:
loglevel.h:128
mb_get_spd_map
void mb_get_spd_map(struct spd_info *spdi)
Definition:
romstage.c:19
mainboard_romstage_entry
void mainboard_romstage_entry(void)
Definition:
romstage.c:6
mb_pre_raminit_setup
void mb_pre_raminit_setup(sysinfo_t *sysinfo)
Definition:
romstage.c:24
sdram_initialize
void sdram_initialize(void)
Definition:
raminit.c:1692
x4x_early_init
void x4x_early_init(void)
Definition:
early_init.c:14
x4x_late_init
void x4x_late_init(void)
Definition:
early_init.c:217
romstage_handoff.h
romstage_handoff_init
int romstage_handoff_init(int is_s3_resume)
Definition:
romstage_handoff.c:42
__weak
const struct smm_save_state_ops *legacy_ops __weak
Definition:
save_state.c:8
southbridge_detect_s3_resume
int southbridge_detect_s3_resume(void)
Definition:
pmclib.c:18
pmclib.h
i82801jx_early_init
void i82801jx_early_init(void)
Definition:
early_init.c:68
u8
uint8_t u8
Definition:
stdint.h:45
raminit.h
x4x.h
BOOT_PATH_WARM_RESET
#define BOOT_PATH_WARM_RESET
Definition:
x4x.h:10
src
northbridge
intel
x4x
romstage.c
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