#include <assert.h>
#include <console/console.h>
#include <device/mmio.h>
#include <delay.h>
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/grf.h>
#include <soc/i2c.h>
#include <soc/soc.h>
#include <stdint.h>
#include <string.h>

Include dependency graph for clock.c:

Data Structures
struct	pll_div

Macros
#define	PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2)

#define	RESETN_DDR_REQ_SHIFT(ch) (8 + (ch) * 4)

#define	RESETN_DDRPHY_REQ_SHIFT(ch) (9 + (ch) * 4)

#define	VCO_MAX_KHZ (3200 * (MHz / KHz))

#define	VCO_MIN_KHZ (800 * (MHz / KHz))

#define	OUTPUT_MAX_KHZ (3200 * (MHz / KHz))

#define	OUTPUT_MIN_KHZ (16 * (MHz / KHz))

#define	PLL_DIV_MIN 16

#define	PLL_DIV_MAX 3200

#define	SPI_CLK_REG_VALUE(bus, clk_div)

#define	I2C_CLK_REG_VALUE(bus, clk_div)

#define	PMU_I2C_CLK_REG_VALUE(bus, clk_div)

Enumerations
enum	{ PLL_FBDIV_MASK = 0xfff , PLL_FBDIV_SHIFT = 0 , PLL_POSTDIV2_MASK = 0x7 , PLL_POSTDIV2_SHIFT = 12 , PLL_POSTDIV1_MASK = 0x7 , PLL_POSTDIV1_SHIFT = 8 , PLL_REFDIV_MASK = 0x3f , PLL_REFDIV_SHIFT = 0 , PLL_LOCK_STATUS_MASK = 1 , PLL_LOCK_STATUS_SHIFT = 31 , PLL_FRACDIV_MASK = 0xffffff , PLL_FRACDIV_SHIFT = 0 , PLL_MODE_MASK = 3 , PLL_MODE_SHIFT = 8 , PLL_MODE_SLOW = 0 , PLL_MODE_NORM , PLL_MODE_DEEP , PLL_DSMPD_MASK = 1 , PLL_DSMPD_SHIFT = 3 , PLL_FRAC_MODE = 0 , PLL_INTEGER_MODE = 1 , PLL_SSMOD_BP_MASK = 1 , PLL_SSMOD_BP_SHIFT = 0 , PLL_SSMOD_DIS_SSCG_MASK = 1 , PLL_SSMOD_DIS_SSCG_SHIFT = 1 , PLL_SSMOD_RESET_MASK = 1 , PLL_SSMOD_RESET_SHIFT = 2 , PLL_SSMOD_DOWNSPEAD_MASK = 1 , PLL_SSMOD_DOWNSPEAD_SHIFT = 3 , PLL_SSMOD_DIVVAL_MASK = 0xf , PLL_SSMOD_DIVVAL_SHIFT = 4 , PLL_SSMOD_SPREADAMP_MASK = 0x1f , PLL_SSMOD_SPREADAMP_SHIFT = 8 , PMU_PCLK_DIV_CON_MASK = 0x1f , PMU_PCLK_DIV_CON_SHIFT = 0 , SPI3_PLL_SEL_MASK = 1 , SPI3_PLL_SEL_SHIFT = 7 , SPI3_PLL_SEL_24M = 0 , SPI3_PLL_SEL_PPLL = 1 , SPI3_DIV_CON_MASK = 0x7f , SPI3_DIV_CON_SHIFT = 0x0 , I2C_DIV_CON_MASK = 0x7f , I2C8_DIV_CON_SHIFT = 8 , I2C0_DIV_CON_SHIFT = 0 , I2C4_DIV_CON_SHIFT = 0 , ACLKM_CORE_DIV_CON_MASK = 0x1f , ACLKM_CORE_DIV_CON_SHIFT = 8 , CLK_CORE_PLL_SEL_MASK = 3 , CLK_CORE_PLL_SEL_SHIFT = 6 , CLK_CORE_PLL_SEL_ALPLL = 0x0 , CLK_CORE_PLL_SEL_ABPLL = 0x1 , CLK_CORE_PLL_SEL_DPLL = 0x10 , CLK_CORE_PLL_SEL_GPLL = 0x11 , CLK_CORE_DIV_MASK = 0x1f , CLK_CORE_DIV_SHIFT = 0 , PCLK_DBG_DIV_MASK = 0x1f , PCLK_DBG_DIV_SHIFT = 0x8 , ATCLK_CORE_DIV_MASK = 0x1f , ATCLK_CORE_DIV_SHIFT = 0 , PCLK_PERIHP_DIV_CON_MASK = 0x7 , PCLK_PERIHP_DIV_CON_SHIFT = 12 , HCLK_PERIHP_DIV_CON_MASK = 3 , HCLK_PERIHP_DIV_CON_SHIFT = 8 , ACLK_PERIHP_PLL_SEL_MASK = 1 , ACLK_PERIHP_PLL_SEL_SHIFT = 7 , ACLK_PERIHP_PLL_SEL_CPLL = 0 , ACLK_PERIHP_PLL_SEL_GPLL = 1 , ACLK_PERIHP_DIV_CON_MASK = 0x1f , ACLK_PERIHP_DIV_CON_SHIFT = 0 , ACLK_EMMC_PLL_SEL_MASK = 0x1 , ACLK_EMMC_PLL_SEL_SHIFT = 7 , ACLK_EMMC_PLL_SEL_GPLL = 0x1 , ACLK_EMMC_DIV_CON_MASK = 0x1f , ACLK_EMMC_DIV_CON_SHIFT = 0 , CLK_EMMC_PLL_MASK = 0x7 , CLK_EMMC_PLL_SHIFT = 8 , CLK_EMMC_PLL_SEL_GPLL = 0x1 , CLK_EMMC_DIV_CON_MASK = 0x7f , CLK_EMMC_DIV_CON_SHIFT = 0 , PCLK_PERILP0_DIV_CON_MASK = 0x7 , PCLK_PERILP0_DIV_CON_SHIFT = 12 , HCLK_PERILP0_DIV_CON_MASK = 3 , HCLK_PERILP0_DIV_CON_SHIFT = 8 , ACLK_PERILP0_PLL_SEL_MASK = 1 , ACLK_PERILP0_PLL_SEL_SHIFT = 7 , ACLK_PERILP0_PLL_SEL_CPLL = 0 , ACLK_PERILP0_PLL_SEL_GPLL = 1 , ACLK_PERILP0_DIV_CON_MASK = 0x1f , ACLK_PERILP0_DIV_CON_SHIFT = 0 , PCLK_PERILP1_DIV_CON_MASK = 0x7 , PCLK_PERILP1_DIV_CON_SHIFT = 8 , HCLK_PERILP1_PLL_SEL_MASK = 1 , HCLK_PERILP1_PLL_SEL_SHIFT = 7 , HCLK_PERILP1_PLL_SEL_CPLL = 0 , HCLK_PERILP1_PLL_SEL_GPLL = 1 , HCLK_PERILP1_DIV_CON_MASK = 0x1f , HCLK_PERILP1_DIV_CON_SHIFT = 0 , CLK_SARADC_DIV_CON_MASK = 0xff , CLK_SARADC_DIV_CON_SHIFT = 8 , CLK_TSADC_SEL_X24M = 0x0 , CLK_TSADC_SEL_MASK = 1 , CLK_TSADC_SEL_SHIFT = 15 , CLK_TSADC_DIV_CON_MASK = 0x3ff , CLK_TSADC_DIV_CON_SHIFT = 0 , CLK_PCLK_EDP_PLL_SEL_MASK = 1 , CLK_PCLK_EDP_PLL_SEL_SHIFT = 15 , CLK_PCLK_EDP_PLL_SEL_CPLL = 0 , CLK_PCLK_EDP_DIV_CON_MASK = 0x3f , CLK_PCLK_EDP_DIV_CON_SHIFT = 8 , ACLK_VOP_PLL_SEL_MASK = 0x3 , ACLK_VOP_PLL_SEL_SHIFT = 6 , ACLK_VOP_PLL_SEL_CPLL = 0x1 , ACLK_VOP_DIV_CON_MASK = 0x1f , ACLK_VOP_DIV_CON_SHIFT = 0 , DCLK_VOP_DCLK_SEL_MASK = 1 , DCLK_VOP_DCLK_SEL_SHIFT = 11 , DCLK_VOP_DCLK_SEL_DIVOUT = 0 , DCLK_VOP_PLL_SEL_MASK = 3 , DCLK_VOP_PLL_SEL_SHIFT = 8 , DCLK_VOP_PLL_SEL_VPLL = 0 , DCLK_VOP_DIV_CON_MASK = 0xff , DCLK_VOP_DIV_CON_SHIFT = 0 , CLK_SPI_PLL_SEL_MASK = 1 , CLK_SPI_PLL_SEL_CPLL = 0 , CLK_SPI_PLL_SEL_GPLL = 1 , CLK_SPI_PLL_DIV_CON_MASK = 0x7f , CLK_SPI5_PLL_DIV_CON_SHIFT = 8 , CLK_SPI5_PLL_SEL_SHIFT = 15 , CLK_SPI1_PLL_SEL_SHIFT = 15 , CLK_SPI1_PLL_DIV_CON_SHIFT = 8 , CLK_SPI0_PLL_SEL_SHIFT = 7 , CLK_SPI0_PLL_DIV_CON_SHIFT = 0 , CLK_SPI4_PLL_SEL_SHIFT = 15 , CLK_SPI4_PLL_DIV_CON_SHIFT = 8 , CLK_SPI2_PLL_SEL_SHIFT = 7 , CLK_SPI2_PLL_DIV_CON_SHIFT = 0 , CLK_I2C_PLL_SEL_MASK = 1 , CLK_I2C_PLL_SEL_CPLL = 0 , CLK_I2C_PLL_SEL_GPLL = 1 , CLK_I2C5_PLL_SEL_SHIFT = 15 , CLK_I2C5_DIV_CON_SHIFT = 8 , CLK_I2C1_PLL_SEL_SHIFT = 7 , CLK_I2C1_DIV_CON_SHIFT = 0 , CLK_I2C6_PLL_SEL_SHIFT = 15 , CLK_I2C6_DIV_CON_SHIFT = 8 , CLK_I2C2_PLL_SEL_SHIFT = 7 , CLK_I2C2_DIV_CON_SHIFT = 0 , CLK_I2C7_PLL_SEL_SHIFT = 15 , CLK_I2C7_DIV_CON_SHIFT = 8 , CLK_I2C3_PLL_SEL_SHIFT = 7 , CLK_I2C3_DIV_CON_SHIFT = 0 }

Functions
static void	rkclk_set_pll (u32 pll_con, const struct pll_div div)

static void	rkclk_set_dpllssc (struct pll_div *dpll_cfg)

static int	pll_para_config (u32 freq_hz, struct pll_div *div)

void	rkclk_init (void)

void	rkclk_configure_cpu (enum apll_frequencies freq, enum cpu_cluster cluster)

void	rkclk_configure_ddr (unsigned int hz)

void	rkclk_ddr_reset (u32 ch, u32 ctl, u32 phy)

void	rkclk_configure_spi (unsigned int bus, unsigned int hz)

uint32_t	rkclk_i2c_clock_for_bus (unsigned int bus)

static u32	clk_gcd (u32 a, u32 b)

void	rkclk_configure_i2s (unsigned int hz)

void	rkclk_configure_saradc (unsigned int hz)

void	rkclk_configure_vop_aclk (u32 vop_id, u32 aclk_hz)

int	rkclk_configure_vop_dclk (u32 vop_id, u32 dclk_hz)

void	rkclk_configure_tsadc (unsigned int hz)

void	rkclk_configure_emmc (void)

int	rkclk_was_watchdog_reset (void)

void	rkclk_configure_edp (unsigned int hz)

void	rkclk_configure_mipi (void)

Variables
static const struct pll_div	gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1)

static const struct pll_div	cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 3, 1)

static const struct pll_div	ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 3, 2, 1)

static const struct pll_div	apll_1512_cfg = PLL_DIVISORS(1512*MHz, 1, 1, 1)

static const struct pll_div	apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 3, 1)

static const struct pll_div *	apll_cfgs []

Macro Definition Documentation

◆ I2C_CLK_REG_VALUE

#define I2C_CLK_REG_VALUE	(	bus,
		clk_div
	)

Value:

                RK_CLRSETBITS(I2C_DIV_CON_MASK << \
                                        CLK_I2C ##bus## _DIV_CON_SHIFT | \
                              CLK_I2C_PLL_SEL_MASK << \
                                        CLK_I2C ##bus## _PLL_SEL_SHIFT, \
                              (clk_div - 1) << \
                                        CLK_I2C ##bus## _DIV_CON_SHIFT | \
                              CLK_I2C_PLL_SEL_GPLL << \
                                        CLK_I2C ##bus## _PLL_SEL_SHIFT)

Definition at line 707 of file clock.c.

◆ OUTPUT_MAX_KHZ

#define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))

Definition at line 258 of file clock.c.

◆ OUTPUT_MIN_KHZ

#define OUTPUT_MIN_KHZ (16 * (MHz / KHz))

Definition at line 259 of file clock.c.

◆ PLL_DIV_MAX

#define PLL_DIV_MAX 3200

Definition at line 265 of file clock.c.

◆ PLL_DIV_MIN

#define PLL_DIV_MIN 16

Definition at line 264 of file clock.c.

◆ PLL_DIVISORS

#define PLL_DIVISORS	(	hz,
		_refdiv,
		_postdiv1,
		_postdiv2
	)

Value:

        {\
        .refdiv = _refdiv,\
        .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
        .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz};\
        _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
                         OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
                         STRINGIFY(hz) " Hz cannot be hit with PLL "\
                         "divisors on line " STRINGIFY(__LINE__))

Definition at line 24 of file clock.c.

◆ PMU_I2C_CLK_REG_VALUE

#define PMU_I2C_CLK_REG_VALUE	(	bus,
		clk_div
	)

Value:

RK_CLRSETBITS(I2C_DIV_CON_MASK << I2C ##bus## _DIV_CON_SHIFT, \

(clk_div - 1) << I2C ##bus## _DIV_CON_SHIFT)

Definition at line 716 of file clock.c.

◆ RESETN_DDR_REQ_SHIFT

#define RESETN_DDR_REQ_SHIFT ( ch ) (8 + (ch) * 4)

Definition at line 252 of file clock.c.

◆ RESETN_DDRPHY_REQ_SHIFT

#define RESETN_DDRPHY_REQ_SHIFT ( ch ) (9 + (ch) * 4)

Definition at line 253 of file clock.c.

◆ SPI_CLK_REG_VALUE

#define SPI_CLK_REG_VALUE	(	bus,
		clk_div
	)

Value:

                RK_CLRSETBITS(CLK_SPI_PLL_SEL_MASK << \
                                        CLK_SPI ##bus## _PLL_SEL_SHIFT | \
                              CLK_SPI_PLL_DIV_CON_MASK << \
                                        CLK_SPI ##bus## _PLL_DIV_CON_SHIFT, \
                              CLK_SPI_PLL_SEL_GPLL << \
                                        CLK_SPI ##bus## _PLL_SEL_SHIFT | \
                              (clk_div - 1) << \
                                        CLK_SPI ##bus## _PLL_DIV_CON_SHIFT)

Definition at line 654 of file clock.c.

◆ VCO_MAX_KHZ

#define VCO_MAX_KHZ (3200 * (MHz / KHz))

Definition at line 256 of file clock.c.

◆ VCO_MIN_KHZ

#define VCO_MIN_KHZ (800 * (MHz / KHz))

Definition at line 257 of file clock.c.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Enumerator
PLL_FBDIV_MASK
PLL_FBDIV_SHIFT
PLL_POSTDIV2_MASK
PLL_POSTDIV2_SHIFT
PLL_POSTDIV1_MASK
PLL_POSTDIV1_SHIFT
PLL_REFDIV_MASK
PLL_REFDIV_SHIFT
PLL_LOCK_STATUS_MASK
PLL_LOCK_STATUS_SHIFT
PLL_FRACDIV_MASK
PLL_FRACDIV_SHIFT
PLL_MODE_MASK
PLL_MODE_SHIFT
PLL_MODE_SLOW
PLL_MODE_NORM
PLL_MODE_DEEP
PLL_DSMPD_MASK
PLL_DSMPD_SHIFT
PLL_FRAC_MODE
PLL_INTEGER_MODE
PLL_SSMOD_BP_MASK
PLL_SSMOD_BP_SHIFT
PLL_SSMOD_DIS_SSCG_MASK
PLL_SSMOD_DIS_SSCG_SHIFT
PLL_SSMOD_RESET_MASK
PLL_SSMOD_RESET_SHIFT
PLL_SSMOD_DOWNSPEAD_MASK
PLL_SSMOD_DOWNSPEAD_SHIFT
PLL_SSMOD_DIVVAL_MASK
PLL_SSMOD_DIVVAL_SHIFT
PLL_SSMOD_SPREADAMP_MASK
PLL_SSMOD_SPREADAMP_SHIFT
PMU_PCLK_DIV_CON_MASK
PMU_PCLK_DIV_CON_SHIFT
SPI3_PLL_SEL_MASK
SPI3_PLL_SEL_SHIFT
SPI3_PLL_SEL_24M
SPI3_PLL_SEL_PPLL
SPI3_DIV_CON_MASK
SPI3_DIV_CON_SHIFT
I2C_DIV_CON_MASK
I2C8_DIV_CON_SHIFT
I2C0_DIV_CON_SHIFT
I2C4_DIV_CON_SHIFT
ACLKM_CORE_DIV_CON_MASK
ACLKM_CORE_DIV_CON_SHIFT
CLK_CORE_PLL_SEL_MASK
CLK_CORE_PLL_SEL_SHIFT
CLK_CORE_PLL_SEL_ALPLL
CLK_CORE_PLL_SEL_ABPLL
CLK_CORE_PLL_SEL_DPLL
CLK_CORE_PLL_SEL_GPLL
CLK_CORE_DIV_MASK
CLK_CORE_DIV_SHIFT
PCLK_DBG_DIV_MASK
PCLK_DBG_DIV_SHIFT
ATCLK_CORE_DIV_MASK
ATCLK_CORE_DIV_SHIFT
PCLK_PERIHP_DIV_CON_MASK
PCLK_PERIHP_DIV_CON_SHIFT
HCLK_PERIHP_DIV_CON_MASK
HCLK_PERIHP_DIV_CON_SHIFT
ACLK_PERIHP_PLL_SEL_MASK
ACLK_PERIHP_PLL_SEL_SHIFT
ACLK_PERIHP_PLL_SEL_CPLL
ACLK_PERIHP_PLL_SEL_GPLL
ACLK_PERIHP_DIV_CON_MASK
ACLK_PERIHP_DIV_CON_SHIFT
ACLK_EMMC_PLL_SEL_MASK
ACLK_EMMC_PLL_SEL_SHIFT
ACLK_EMMC_PLL_SEL_GPLL
ACLK_EMMC_DIV_CON_MASK
ACLK_EMMC_DIV_CON_SHIFT
CLK_EMMC_PLL_MASK
CLK_EMMC_PLL_SHIFT
CLK_EMMC_PLL_SEL_GPLL
CLK_EMMC_DIV_CON_MASK
CLK_EMMC_DIV_CON_SHIFT
PCLK_PERILP0_DIV_CON_MASK
PCLK_PERILP0_DIV_CON_SHIFT
HCLK_PERILP0_DIV_CON_MASK
HCLK_PERILP0_DIV_CON_SHIFT
ACLK_PERILP0_PLL_SEL_MASK
ACLK_PERILP0_PLL_SEL_SHIFT
ACLK_PERILP0_PLL_SEL_CPLL
ACLK_PERILP0_PLL_SEL_GPLL
ACLK_PERILP0_DIV_CON_MASK
ACLK_PERILP0_DIV_CON_SHIFT
PCLK_PERILP1_DIV_CON_MASK
PCLK_PERILP1_DIV_CON_SHIFT
HCLK_PERILP1_PLL_SEL_MASK
HCLK_PERILP1_PLL_SEL_SHIFT
HCLK_PERILP1_PLL_SEL_CPLL
HCLK_PERILP1_PLL_SEL_GPLL
HCLK_PERILP1_DIV_CON_MASK
HCLK_PERILP1_DIV_CON_SHIFT
CLK_SARADC_DIV_CON_MASK
CLK_SARADC_DIV_CON_SHIFT
CLK_TSADC_SEL_X24M
CLK_TSADC_SEL_MASK
CLK_TSADC_SEL_SHIFT
CLK_TSADC_DIV_CON_MASK
CLK_TSADC_DIV_CON_SHIFT
CLK_PCLK_EDP_PLL_SEL_MASK
CLK_PCLK_EDP_PLL_SEL_SHIFT
CLK_PCLK_EDP_PLL_SEL_CPLL
CLK_PCLK_EDP_DIV_CON_MASK
CLK_PCLK_EDP_DIV_CON_SHIFT
ACLK_VOP_PLL_SEL_MASK
ACLK_VOP_PLL_SEL_SHIFT
ACLK_VOP_PLL_SEL_CPLL
ACLK_VOP_DIV_CON_MASK
ACLK_VOP_DIV_CON_SHIFT
DCLK_VOP_DCLK_SEL_MASK
DCLK_VOP_DCLK_SEL_SHIFT
DCLK_VOP_DCLK_SEL_DIVOUT
DCLK_VOP_PLL_SEL_MASK
DCLK_VOP_PLL_SEL_SHIFT
DCLK_VOP_PLL_SEL_VPLL
DCLK_VOP_DIV_CON_MASK
DCLK_VOP_DIV_CON_SHIFT
CLK_SPI_PLL_SEL_MASK
CLK_SPI_PLL_SEL_CPLL
CLK_SPI_PLL_SEL_GPLL
CLK_SPI_PLL_DIV_CON_MASK
CLK_SPI5_PLL_DIV_CON_SHIFT
CLK_SPI5_PLL_SEL_SHIFT
CLK_SPI1_PLL_SEL_SHIFT
CLK_SPI1_PLL_DIV_CON_SHIFT
CLK_SPI0_PLL_SEL_SHIFT
CLK_SPI0_PLL_DIV_CON_SHIFT
CLK_SPI4_PLL_SEL_SHIFT
CLK_SPI4_PLL_DIV_CON_SHIFT
CLK_SPI2_PLL_SEL_SHIFT
CLK_SPI2_PLL_DIV_CON_SHIFT
CLK_I2C_PLL_SEL_MASK
CLK_I2C_PLL_SEL_CPLL
CLK_I2C_PLL_SEL_GPLL
CLK_I2C5_PLL_SEL_SHIFT
CLK_I2C5_DIV_CON_SHIFT
CLK_I2C1_PLL_SEL_SHIFT
CLK_I2C1_DIV_CON_SHIFT
CLK_I2C6_PLL_SEL_SHIFT
CLK_I2C6_DIV_CON_SHIFT
CLK_I2C2_PLL_SEL_SHIFT
CLK_I2C2_DIV_CON_SHIFT
CLK_I2C7_PLL_SEL_SHIFT
CLK_I2C7_DIV_CON_SHIFT
CLK_I2C3_PLL_SEL_SHIFT
CLK_I2C3_DIV_CON_SHIFT

Definition at line 45 of file clock.c.

Function Documentation

◆ clk_gcd()

static u32 clk_gcd	(	u32	a,
		u32	b
	)

static

Definition at line 779 of file clock.c.

Referenced by rkclk_configure_i2s().

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◆ pll_para_config()

static int pll_para_config	(	u32	freq_hz,
		struct pll_div *	div
	)

static

Definition at line 397 of file clock.c.

References BIOS_ERR, DIV_ROUND_UP, pll_div::fbdiv, KHz, MHz, OSC_HZ, pll_div::postdiv1, pll_div::postdiv2, printk, pll_div::refdiv, VCO_MAX_KHZ, and VCO_MIN_KHZ.

Referenced by rkclk_configure_vop_dclk().

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◆ rkclk_configure_cpu()

void rkclk_configure_cpu	(	enum apll_frequencies	freq,
		enum cpu_cluster	cluster
	)

Definition at line 566 of file clock.c.

References ACLKM_CORE_DIV_CON_MASK, ACLKM_CORE_DIV_CON_SHIFT, ACLKM_CORE_HZ, apll_cfgs, ATCLK_CORE_DIV_MASK, ATCLK_CORE_DIV_SHIFT, ATCLK_CORE_HZ, CLK_CORE_DIV_MASK, CLK_CORE_DIV_SHIFT, CLK_CORE_PLL_SEL_ABPLL, CLK_CORE_PLL_SEL_ALPLL, CLK_CORE_PLL_SEL_MASK, CLK_CORE_PLL_SEL_SHIFT, CPU_CLUSTER_BIG, CPU_CLUSTER_LITTLE, cru_ptr, DIV_ROUND_UP, pll_div::freq, PCLK_DBG_DIV_MASK, PCLK_DBG_DIV_SHIFT, PCLK_DBG_HZ, RK_CLRSETBITS, rkclk_set_pll(), and write32().

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◆ rkclk_configure_ddr()

void rkclk_configure_ddr ( unsigned int hz )

Definition at line 609 of file clock.c.

References CONFIG, cru_ptr, rk3399_pmusgrf_regs::ddr_rgn_con, die(), MHz, pll_div::refdiv, rk3399_pmusgrf, rkclk_set_dpllssc(), rkclk_set_pll(), and write32().

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◆ rkclk_configure_edp()

void rkclk_configure_edp ( unsigned int hz )

Definition at line 927 of file clock.c.

References assert, CLK_PCLK_EDP_DIV_CON_MASK, CLK_PCLK_EDP_DIV_CON_SHIFT, CLK_PCLK_EDP_PLL_SEL_CPLL, CLK_PCLK_EDP_PLL_SEL_MASK, CLK_PCLK_EDP_PLL_SEL_SHIFT, CPLL_HZ, cru_ptr, RK_CLRSETBITS, and write32().

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◆ rkclk_configure_emmc()

void rkclk_configure_emmc ( void )

Definition at line 892 of file clock.c.

References ACLK_EMMC_DIV_CON_MASK, ACLK_EMMC_DIV_CON_SHIFT, ACLK_EMMC_PLL_SEL_GPLL, ACLK_EMMC_PLL_SEL_MASK, ACLK_EMMC_PLL_SEL_SHIFT, assert, CLK_EMMC_DIV_CON_MASK, CLK_EMMC_DIV_CON_SHIFT, CLK_EMMC_PLL_MASK, CLK_EMMC_PLL_SEL_GPLL, CLK_EMMC_PLL_SHIFT, cru_ptr, GPLL_HZ, KHz, RK_CLRSETBITS, and write32().

Referenced by configure_emmc().

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◆ rkclk_configure_i2s()

void rkclk_configure_i2s ( unsigned int hz )

clk_i2s0_sel: divider output from fraction clk_i2s0_pll_sel source clock: cpll clk_i2s0_div_con: 1 (div+1)

clk_i2sout_sel clk_i2s clk_i2s_ch_sel: clk_i2s0

Definition at line 789 of file clock.c.

References assert, clk_gcd(), CPLL_HZ, cru_ptr, RK_CLRBITS, RK_CLRSETBITS, and write32().

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◆ rkclk_configure_mipi()

void rkclk_configure_mipi ( void )

Definition at line 945 of file clock.c.

References cru_ptr, RK_CLRBITS, and write32().

Referenced by rk_display_init().

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◆ rkclk_configure_saradc()

void rkclk_configure_saradc ( unsigned int hz )

Definition at line 823 of file clock.c.

References assert, CLK_SARADC_DIV_CON_MASK, CLK_SARADC_DIV_CON_SHIFT, cru_ptr, MHz, RK_CLRSETBITS, and write32().

Referenced by get_saradc_value().

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◆ rkclk_configure_spi()

void rkclk_configure_spi	(	unsigned int	bus,
		unsigned int	hz
	)

Definition at line 664 of file clock.c.

References assert, BIOS_ERR, cru_ptr, GPLL_HZ, rk3399_pmucru_reg::pmucru_clksel, pmucru_ptr, PPLL_HZ, printk, RK_CLRSETBITS, SPI3_DIV_CON_MASK, SPI3_DIV_CON_SHIFT, SPI3_PLL_SEL_MASK, SPI3_PLL_SEL_PPLL, SPI3_PLL_SEL_SHIFT, SPI_CLK_REG_VALUE, and write32().

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◆ rkclk_configure_tsadc()

void rkclk_configure_tsadc ( unsigned int hz )

Definition at line 877 of file clock.c.

References assert, CLK_TSADC_DIV_CON_MASK, CLK_TSADC_DIV_CON_SHIFT, CLK_TSADC_SEL_MASK, CLK_TSADC_SEL_SHIFT, CLK_TSADC_SEL_X24M, cru_ptr, OSC_HZ, RK_CLRSETBITS, and write32().

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◆ rkclk_configure_vop_aclk()

void rkclk_configure_vop_aclk	(	u32	vop_id,
		u32	aclk_hz
	)

Definition at line 837 of file clock.c.

References ACLK_VOP_DIV_CON_MASK, ACLK_VOP_DIV_CON_SHIFT, ACLK_VOP_PLL_SEL_CPLL, ACLK_VOP_PLL_SEL_MASK, ACLK_VOP_PLL_SEL_SHIFT, assert, CPLL_HZ, cru_ptr, RK_CLRSETBITS, and write32().

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◆ rkclk_configure_vop_dclk()

int rkclk_configure_vop_dclk	(	u32	vop_id,
		u32	dclk_hz
	)

Definition at line 854 of file clock.c.

References cru_ptr, DCLK_VOP_DCLK_SEL_DIVOUT, DCLK_VOP_DCLK_SEL_MASK, DCLK_VOP_DCLK_SEL_SHIFT, DCLK_VOP_DIV_CON_MASK, DCLK_VOP_DIV_CON_SHIFT, DCLK_VOP_PLL_SEL_MASK, DCLK_VOP_PLL_SEL_SHIFT, DCLK_VOP_PLL_SEL_VPLL, pll_para_config(), RK_CLRSETBITS, rkclk_set_pll(), and write32().

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◆ rkclk_ddr_reset()

void rkclk_ddr_reset	(	u32	ch,
		u32	ctl,
		u32	phy
	)

Definition at line 647 of file clock.c.

References ch, cru_ptr, RESETN_DDR_REQ_SHIFT, RESETN_DDRPHY_REQ_SHIFT, RK_CLRSETBITS, and write32().

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◆ rkclk_i2c_clock_for_bus()

uint32_t rkclk_i2c_clock_for_bus ( unsigned int bus )

Definition at line 720 of file clock.c.

References assert, cru_ptr, die(), GPLL_HZ, I2C_CLK_REG_VALUE, MHz, PMU_I2C_CLK_REG_VALUE, rk3399_pmucru_reg::pmucru_clksel, pmucru_ptr, PPLL_HZ, and write32().

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◆ rkclk_init()

void rkclk_init ( void )

Definition at line 461 of file clock.c.

References ACLK_PERIHP_DIV_CON_MASK, ACLK_PERIHP_DIV_CON_SHIFT, ACLK_PERIHP_PLL_SEL_GPLL, ACLK_PERIHP_PLL_SEL_MASK, ACLK_PERIHP_PLL_SEL_SHIFT, ACLK_PERILP0_DIV_CON_MASK, ACLK_PERILP0_DIV_CON_SHIFT, ACLK_PERILP0_PLL_SEL_GPLL, ACLK_PERILP0_PLL_SEL_MASK, ACLK_PERILP0_PLL_SEL_SHIFT, assert, cpll_init_cfg, cru_ptr, GPLL_HZ, gpll_init_cfg, HCLK_PERIHP_DIV_CON_MASK, HCLK_PERIHP_DIV_CON_SHIFT, HCLK_PERILP0_DIV_CON_MASK, HCLK_PERILP0_DIV_CON_SHIFT, HCLK_PERILP1_DIV_CON_MASK, HCLK_PERILP1_DIV_CON_SHIFT, HCLK_PERILP1_PLL_SEL_GPLL, HCLK_PERILP1_PLL_SEL_MASK, HCLK_PERILP1_PLL_SEL_SHIFT, PCLK_PERIHP_DIV_CON_MASK, PCLK_PERIHP_DIV_CON_SHIFT, PCLK_PERILP0_DIV_CON_MASK, PCLK_PERILP0_DIV_CON_SHIFT, PCLK_PERILP1_DIV_CON_MASK, PCLK_PERILP1_DIV_CON_SHIFT, PERIHP_ACLK_HZ, PERIHP_HCLK_HZ, PERIHP_PCLK_HZ, PERILP0_ACLK_HZ, PERILP0_HCLK_HZ, PERILP0_PCLK_HZ, PERILP1_HCLK_HZ, PERILP1_PCLK_HZ, PMU_PCLK_DIV_CON_MASK, PMU_PCLK_DIV_CON_SHIFT, PMU_PCLK_HZ, rk3399_pmucru_reg::pmucru_clksel, pmucru_ptr, rk3399_pmucru_reg::ppll_con, PPLL_HZ, ppll_init_cfg, RK_CLRSETBITS, rkclk_set_pll(), and write32().

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◆ rkclk_set_dpllssc()

static void rkclk_set_dpllssc ( struct pll_div * dpll_cfg )

static

Definition at line 336 of file clock.c.

References assert, clrsetbits32, cru_ptr, KHz, OSC_HZ, PLL_DSMPD_MASK, PLL_DSMPD_SHIFT, PLL_FRAC_MODE, PLL_FRACDIV_MASK, PLL_FRACDIV_SHIFT, PLL_SSMOD_BP_MASK, PLL_SSMOD_BP_SHIFT, PLL_SSMOD_DIS_SSCG_MASK, PLL_SSMOD_DIS_SSCG_SHIFT, PLL_SSMOD_DIVVAL_MASK, PLL_SSMOD_DIVVAL_SHIFT, PLL_SSMOD_RESET_MASK, PLL_SSMOD_RESET_SHIFT, PLL_SSMOD_SPREADAMP_MASK, PLL_SSMOD_SPREADAMP_SHIFT, pll_div::refdiv, RK_CLRBITS, RK_CLRSETBITS, udelay(), and write32().

Referenced by rkclk_configure_ddr().

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◆ rkclk_set_pll()

static void rkclk_set_pll	(	u32 *	pll_con,
		const struct pll_div *	div
	)

static

Definition at line 281 of file clock.c.

References assert, BIOS_DEBUG, pll_div::fbdiv, OSC_HZ, OUTPUT_MAX_KHZ, OUTPUT_MIN_KHZ, PLL_DIV_MAX, PLL_DIV_MIN, PLL_DSMPD_MASK, PLL_DSMPD_SHIFT, PLL_FBDIV_MASK, PLL_FBDIV_SHIFT, PLL_INTEGER_MODE, PLL_LOCK_STATUS_SHIFT, PLL_MODE_MASK, PLL_MODE_NORM, PLL_MODE_SHIFT, PLL_MODE_SLOW, PLL_POSTDIV1_MASK, PLL_POSTDIV1_SHIFT, PLL_POSTDIV2_MASK, PLL_POSTDIV2_SHIFT, PLL_REFDIV_MASK, PLL_REFDIV_SHIFT, pll_div::postdiv1, pll_div::postdiv2, printk, read32(), pll_div::refdiv, RK_CLRSETBITS, udelay(), VCO_MAX_KHZ, VCO_MIN_KHZ, and write32().

Referenced by rkclk_configure_cpu(), rkclk_configure_ddr(), rkclk_configure_vop_dclk(), and rkclk_init().

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◆ rkclk_was_watchdog_reset()

int rkclk_was_watchdog_reset ( void )

Definition at line 921 of file clock.c.

References cru_ptr, and read32().

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Variable Documentation

◆ apll_1512_cfg

const struct pll_div apll_1512_cfg = PLL_DIVISORS(1512*MHz, 1, 1, 1)

static

Definition at line 1 of file clock.c.

◆ apll_600_cfg

const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 3, 1)

static

Definition at line 1 of file clock.c.

◆ apll_cfgs

const struct pll_div* apll_cfgs[]

static

Initial value:

= {
        [APLL_1512_MHZ] = &apll_1512_cfg,
        [APLL_600_MHZ] = &apll_600_cfg,
}

Definition at line 40 of file clock.c.

Referenced by rkclk_configure_cpu().

◆ cpll_init_cfg

const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 3, 1)

static

Definition at line 1 of file clock.c.

Referenced by rkclk_init().

◆ gpll_init_cfg

const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1)

static

Definition at line 1 of file clock.c.

Referenced by rkclk_init().

◆ ppll_init_cfg

const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 3, 2, 1)

static

Definition at line 1 of file clock.c.

Referenced by rkclk_init().

Data Structures

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

◆ I2C_CLK_REG_VALUE

◆ OUTPUT_MAX_KHZ

◆ OUTPUT_MIN_KHZ

◆ PLL_DIV_MAX

◆ PLL_DIV_MIN

◆ PLL_DIVISORS

◆ PMU_I2C_CLK_REG_VALUE

◆ RESETN_DDR_REQ_SHIFT

◆ RESETN_DDRPHY_REQ_SHIFT

◆ SPI_CLK_REG_VALUE

◆ VCO_MAX_KHZ

◆ VCO_MIN_KHZ

Enumeration Type Documentation

◆ anonymous enum

Function Documentation

◆ clk_gcd()

◆ pll_para_config()

◆ rkclk_configure_cpu()

◆ rkclk_configure_ddr()

◆ rkclk_configure_edp()

◆ rkclk_configure_emmc()

◆ rkclk_configure_i2s()

◆ rkclk_configure_mipi()

◆ rkclk_configure_saradc()

◆ rkclk_configure_spi()

◆ rkclk_configure_tsadc()

◆ rkclk_configure_vop_aclk()

◆ rkclk_configure_vop_dclk()

◆ rkclk_ddr_reset()

◆ rkclk_i2c_clock_for_bus()

◆ rkclk_init()

◆ rkclk_set_dpllssc()

◆ rkclk_set_pll()

◆ rkclk_was_watchdog_reset()

Variable Documentation

◆ apll_1512_cfg

◆ apll_600_cfg

◆ apll_cfgs

◆ cpll_init_cfg

◆ gpll_init_cfg

◆ ppll_init_cfg