coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
Data Structures | Macros | Enumerations | Functions | Variables
clock.h File Reference
#include <soc/addressmap.h>
#include <types.h>
Include dependency graph for clock.h:

Go to the source code of this file.

Data Structures

struct  rk3399_pmucru_reg
 
struct  rk3399_cru_reg
 

Macros

#define OSC_HZ   (24*MHz)
 
#define GPLL_HZ   (594*MHz)
 
#define CPLL_HZ   (800*MHz)
 
#define PPLL_HZ   (676*MHz)
 
#define PMU_PCLK_HZ   96571428
 
#define ACLKM_CORE_HZ   (300*MHz)
 
#define ATCLK_CORE_HZ   (300*MHz)
 
#define PCLK_DBG_HZ   (100*MHz)
 
#define PERIHP_ACLK_HZ   (148500*KHz)
 
#define PERIHP_HCLK_HZ   (148500*KHz)
 
#define PERIHP_PCLK_HZ   (37125*KHz)
 
#define PERILP0_ACLK_HZ   (99000*KHz)
 
#define PERILP0_HCLK_HZ   (99000*KHz)
 
#define PERILP0_PCLK_HZ   (49500*KHz)
 
#define PERILP1_HCLK_HZ   (99000*KHz)
 
#define PERILP1_PCLK_HZ   (99000*KHz)
 
#define PWM_CLOCK_HZ   PMU_PCLK_HZ
 

Enumerations

enum  apll_frequencies {
  APLL_1800_MHZ , APLL_1416_MHZ , APLL_600_MHZ , APLL_1512_MHZ ,
  APLL_600_MHZ
}
 
enum  cpu_cluster { CPU_CLUSTER_LITTLE , CPU_CLUSTER_BIG }
 

Functions

 check_member (rk3399_pmucru_reg, pmucru_gatedis_con[1], 0x134)
 
 check_member (rk3399_cru_reg, sdio1_con[1], 0x594)
 
void rkclk_init (void)
 
int rkclk_configure_vop_dclk (u32 vop_id, u32 dclk_hz)
 
void rkclk_configure_cpu (enum apll_frequencies freq, enum cpu_cluster cluster)
 
void rkclk_configure_ddr (unsigned int hz)
 
void rkclk_configure_emmc (void)
 
void rkclk_configure_i2s (unsigned int hz)
 
void rkclk_configure_saradc (unsigned int hz)
 
void rkclk_configure_spi (unsigned int bus, unsigned int hz)
 
void rkclk_configure_tsadc (unsigned int hz)
 
void rkclk_configure_vop_aclk (u32 vop_id, u32 aclk_hz)
 
void rkclk_ddr_reset (u32 ch, u32 ctl, u32 phy)
 
int rkclk_was_watchdog_reset (void)
 
uint32_t rkclk_i2c_clock_for_bus (unsigned int bus)
 
void rkclk_configure_edp (unsigned int hz)
 
void rkclk_configure_mipi (void)
 

Variables

static struct rk3399_pmucru_reg *const pmucru_ptr = (void *)PMUCRU_BASE
 
static struct rk3399_cru_reg *const cru_ptr = (void *)CRU_BASE
 

Macro Definition Documentation

◆ ACLKM_CORE_HZ

#define ACLKM_CORE_HZ   (300*MHz)

Definition at line 69 of file clock.h.

◆ ATCLK_CORE_HZ

#define ATCLK_CORE_HZ   (300*MHz)

Definition at line 70 of file clock.h.

◆ CPLL_HZ

#define CPLL_HZ   (800*MHz)

Definition at line 64 of file clock.h.

◆ GPLL_HZ

#define GPLL_HZ   (594*MHz)

Definition at line 63 of file clock.h.

◆ OSC_HZ

#define OSC_HZ   (24*MHz)

Definition at line 62 of file clock.h.

◆ PCLK_DBG_HZ

#define PCLK_DBG_HZ   (100*MHz)

Definition at line 71 of file clock.h.

◆ PERIHP_ACLK_HZ

#define PERIHP_ACLK_HZ   (148500*KHz)

Definition at line 73 of file clock.h.

◆ PERIHP_HCLK_HZ

#define PERIHP_HCLK_HZ   (148500*KHz)

Definition at line 74 of file clock.h.

◆ PERIHP_PCLK_HZ

#define PERIHP_PCLK_HZ   (37125*KHz)

Definition at line 75 of file clock.h.

◆ PERILP0_ACLK_HZ

#define PERILP0_ACLK_HZ   (99000*KHz)

Definition at line 77 of file clock.h.

◆ PERILP0_HCLK_HZ

#define PERILP0_HCLK_HZ   (99000*KHz)

Definition at line 78 of file clock.h.

◆ PERILP0_PCLK_HZ

#define PERILP0_PCLK_HZ   (49500*KHz)

Definition at line 79 of file clock.h.

◆ PERILP1_HCLK_HZ

#define PERILP1_HCLK_HZ   (99000*KHz)

Definition at line 81 of file clock.h.

◆ PERILP1_PCLK_HZ

#define PERILP1_PCLK_HZ   (99000*KHz)

Definition at line 82 of file clock.h.

◆ PMU_PCLK_HZ

#define PMU_PCLK_HZ   96571428

Definition at line 67 of file clock.h.

◆ PPLL_HZ

#define PPLL_HZ   (676*MHz)

Definition at line 65 of file clock.h.

◆ PWM_CLOCK_HZ

#define PWM_CLOCK_HZ   PMU_PCLK_HZ

Definition at line 84 of file clock.h.

Enumeration Type Documentation

◆ apll_frequencies

enum apll_frequencies
Enumerator
APLL_1800_MHZ 
APLL_1416_MHZ 
APLL_600_MHZ 
APLL_1512_MHZ 
APLL_600_MHZ 

Definition at line 86 of file clock.h.

◆ cpu_cluster

enum cpu_cluster
Enumerator
CPU_CLUSTER_LITTLE 
CPU_CLUSTER_BIG 

Definition at line 91 of file clock.h.

Function Documentation

◆ check_member() [1/2]

check_member ( rk3399_cru_reg  ,
sdio1_con  [1],
0x594   
)

◆ check_member() [2/2]

check_member ( rk3399_pmucru_reg  ,
pmucru_gatedis_con  [1],
0x134   
)

◆ rkclk_configure_cpu()

void rkclk_configure_cpu ( enum apll_frequencies  freq,
enum cpu_cluster  cluster 
)

Definition at line 566 of file clock.c.

References ACLKM_CORE_DIV_CON_MASK, ACLKM_CORE_DIV_CON_SHIFT, ACLKM_CORE_HZ, apll_cfgs, ATCLK_CORE_DIV_MASK, ATCLK_CORE_DIV_SHIFT, ATCLK_CORE_HZ, CLK_CORE_DIV_MASK, CLK_CORE_DIV_SHIFT, CLK_CORE_PLL_SEL_ABPLL, CLK_CORE_PLL_SEL_ALPLL, CLK_CORE_PLL_SEL_MASK, CLK_CORE_PLL_SEL_SHIFT, CPU_CLUSTER_BIG, CPU_CLUSTER_LITTLE, cru_ptr, DIV_ROUND_UP, pll_div::freq, PCLK_DBG_DIV_MASK, PCLK_DBG_DIV_SHIFT, PCLK_DBG_HZ, RK_CLRSETBITS, rkclk_set_pll(), and write32().

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◆ rkclk_configure_ddr()

void rkclk_configure_ddr ( unsigned int  hz)

Definition at line 349 of file clock.c.

References CONFIG, rk3288_cru_reg::cru_dpll_con, rk3288_cru_reg::cru_mode_con, cru_ptr, rk3399_pmusgrf_regs::ddr_rgn_con, die(), DPLL_MODE_MSK, DPLL_MODE_NORM, DPLL_MODE_SLOW, MHz, pll_div::nf, read32(), pll_div::refdiv, rk3288_grf, rk3399_pmusgrf, RK_CLRSETBITS, rkclk_set_dpllssc(), rkclk_set_pll(), rk3288_grf_regs::soc_status, SOCSTS_DPLL_LOCK, udelay(), and write32().

Referenced by sdram_init().

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◆ rkclk_configure_edp()

void rkclk_configure_edp ( unsigned int  hz)

Definition at line 927 of file clock.c.

References assert, CLK_PCLK_EDP_DIV_CON_MASK, CLK_PCLK_EDP_DIV_CON_SHIFT, CLK_PCLK_EDP_PLL_SEL_CPLL, CLK_PCLK_EDP_PLL_SEL_MASK, CLK_PCLK_EDP_PLL_SEL_SHIFT, CPLL_HZ, cru_ptr, RK_CLRSETBITS, and write32().

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◆ rkclk_configure_emmc()

void rkclk_configure_emmc ( void  )

Definition at line 892 of file clock.c.

References ACLK_EMMC_DIV_CON_MASK, ACLK_EMMC_DIV_CON_SHIFT, ACLK_EMMC_PLL_SEL_GPLL, ACLK_EMMC_PLL_SEL_MASK, ACLK_EMMC_PLL_SEL_SHIFT, assert, CLK_EMMC_DIV_CON_MASK, CLK_EMMC_DIV_CON_SHIFT, CLK_EMMC_PLL_MASK, CLK_EMMC_PLL_SEL_GPLL, CLK_EMMC_PLL_SHIFT, cru_ptr, GPLL_HZ, KHz, RK_CLRSETBITS, and write32().

Referenced by configure_emmc().

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◆ rkclk_configure_i2s()

void rkclk_configure_i2s ( unsigned int  hz)

clk_i2s0_sel: divider output from fraction clk_i2s0_pll_sel source clock: cpll clk_i2s0_div_con: 1 (div+1)

clk_i2sout_sel clk_i2s clk_i2s_ch_sel: clk_i2s0

Definition at line 451 of file clock.c.

References assert, clk_gcd(), CPLL_HZ, rk3288_cru_reg::cru_clksel_con, cru_ptr, GPLL_HZ, RK_CLRBITS, RK_CLRSETBITS, and write32().

Referenced by configure_codec(), and configure_i2s().

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◆ rkclk_configure_mipi()

void rkclk_configure_mipi ( void  )

Definition at line 945 of file clock.c.

References cru_ptr, RK_CLRBITS, and write32().

Referenced by rk_display_init().

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◆ rkclk_configure_saradc()

void rkclk_configure_saradc ( unsigned int  hz)

Definition at line 823 of file clock.c.

References assert, CLK_SARADC_DIV_CON_MASK, CLK_SARADC_DIV_CON_SHIFT, cru_ptr, MHz, RK_CLRSETBITS, and write32().

Referenced by get_saradc_value().

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◆ rkclk_configure_spi()

void rkclk_configure_spi ( unsigned int  bus,
unsigned int  hz 
)

Definition at line 414 of file clock.c.

References assert, BIOS_ERR, rk3288_cru_reg::cru_clksel_con, cru_ptr, GPLL_HZ, rk3399_pmucru_reg::pmucru_clksel, pmucru_ptr, PPLL_HZ, printk, RK_CLRSETBITS, SPI3_DIV_CON_MASK, SPI3_DIV_CON_SHIFT, SPI3_PLL_SEL_MASK, SPI3_PLL_SEL_PPLL, SPI3_PLL_SEL_SHIFT, SPI_CLK_REG_VALUE, and write32().

Referenced by rockchip_spi_init().

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◆ rkclk_configure_tsadc()

void rkclk_configure_tsadc ( unsigned int  hz)

Definition at line 482 of file clock.c.

References assert, CLK_TSADC_DIV_CON_MASK, CLK_TSADC_DIV_CON_SHIFT, CLK_TSADC_SEL_MASK, CLK_TSADC_SEL_SHIFT, CLK_TSADC_SEL_X24M, rk3288_cru_reg::cru_clksel_con, cru_ptr, KHz, OSC_HZ, RK_CLRSETBITS, and write32().

Referenced by tsadc_init().

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◆ rkclk_configure_vop_aclk()

void rkclk_configure_vop_aclk ( u32  vop_id,
u32  aclk_hz 
)

Definition at line 587 of file clock.c.

References ACLK_VOP_DIV_CON_MASK, ACLK_VOP_DIV_CON_SHIFT, ACLK_VOP_PLL_SEL_CPLL, ACLK_VOP_PLL_SEL_MASK, ACLK_VOP_PLL_SEL_SHIFT, assert, CPLL_HZ, rk3288_cru_reg::cru_clksel_con, cru_ptr, RK_CLRSETBITS, and write32().

Referenced by rk_display_init().

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◆ rkclk_configure_vop_dclk()

int rkclk_configure_vop_dclk ( u32  vop_id,
u32  dclk_hz 
)

Definition at line 610 of file clock.c.

References rk3288_cru_reg::cru_clksel_con, rk3288_cru_reg::cru_mode_con, rk3288_cru_reg::cru_npll_con, cru_ptr, DCLK_VOP_DCLK_SEL_DIVOUT, DCLK_VOP_DCLK_SEL_MASK, DCLK_VOP_DCLK_SEL_SHIFT, DCLK_VOP_DIV_CON_MASK, DCLK_VOP_DIV_CON_SHIFT, DCLK_VOP_PLL_SEL_MASK, DCLK_VOP_PLL_SEL_SHIFT, DCLK_VOP_PLL_SEL_VPLL, NPLL_MODE_MSK, NPLL_MODE_NORM, NPLL_MODE_SLOW, pll_para_config(), read32(), rk3288_grf, RK_CLRSETBITS, rkclk_set_pll(), rk3288_grf_regs::soc_status, SOCSTS_NPLL_LOCK, udelay(), and write32().

Referenced by rk_display_init().

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◆ rkclk_ddr_reset()

void rkclk_ddr_reset ( u32  ch,
u32  ctl,
u32  phy 
)

Definition at line 388 of file clock.c.

References ch, cru_ptr, rk3288_cru_reg::cru_softrst_con, RESETN_DDR_REQ_SHIFT, RESETN_DDRPHY_REQ_SHIFT, RK_CLRSETBITS, and write32().

Referenced by phy_pctrl_reset().

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◆ rkclk_i2c_clock_for_bus()

uint32_t rkclk_i2c_clock_for_bus ( unsigned int  bus)

Definition at line 658 of file clock.c.

References assert, cru_ptr, die(), GPLL_HZ, I2C_CLK_REG_VALUE, MHz, PD_BUS_PCLK_HZ, PERI_PCLK_HZ, PMU_I2C_CLK_REG_VALUE, rk3399_pmucru_reg::pmucru_clksel, pmucru_ptr, PPLL_HZ, and write32().

Referenced by i2c_init().

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◆ rkclk_init()

void rkclk_init ( void  )

Definition at line 232 of file clock.c.

References ACLK_PERIHP_DIV_CON_MASK, ACLK_PERIHP_DIV_CON_SHIFT, ACLK_PERIHP_PLL_SEL_GPLL, ACLK_PERIHP_PLL_SEL_MASK, ACLK_PERIHP_PLL_SEL_SHIFT, ACLK_PERILP0_DIV_CON_MASK, ACLK_PERILP0_DIV_CON_SHIFT, ACLK_PERILP0_PLL_SEL_GPLL, ACLK_PERILP0_PLL_SEL_MASK, ACLK_PERILP0_PLL_SEL_SHIFT, assert, cpll_init_cfg, CPLL_MODE_MSK, CPLL_MODE_NORM, CPLL_MODE_SLOW, rk3288_cru_reg::cru_clksel_con, rk3288_cru_reg::cru_cpll_con, rk3288_cru_reg::cru_gpll_con, rk3288_cru_reg::cru_mode_con, cru_ptr, GPLL_HZ, gpll_init_cfg, GPLL_MODE_MSK, GPLL_MODE_NORM, GPLL_MODE_SLOW, HCLK_PERIHP_DIV_CON_MASK, HCLK_PERIHP_DIV_CON_SHIFT, HCLK_PERILP0_DIV_CON_MASK, HCLK_PERILP0_DIV_CON_SHIFT, HCLK_PERILP1_DIV_CON_MASK, HCLK_PERILP1_DIV_CON_SHIFT, HCLK_PERILP1_PLL_SEL_GPLL, HCLK_PERILP1_PLL_SEL_MASK, HCLK_PERILP1_PLL_SEL_SHIFT, log2(), PCLK_PERIHP_DIV_CON_MASK, PCLK_PERIHP_DIV_CON_SHIFT, PCLK_PERILP0_DIV_CON_MASK, PCLK_PERILP0_DIV_CON_SHIFT, PCLK_PERILP1_DIV_CON_MASK, PCLK_PERILP1_DIV_CON_SHIFT, PD_BUS_ACLK_DIV0_MASK, PD_BUS_ACLK_DIV0_SHIFT, PD_BUS_ACLK_DIV1_MASK, PD_BUS_ACLK_HZ, PD_BUS_HCLK_DIV_MSK, PD_BUS_HCLK_DIV_SHIFT, PD_BUS_HCLK_HZ, PD_BUS_PCLK_DIV_MSK, PD_BUS_PCLK_DIV_SHIFT, PD_BUS_PCLK_HZ, PD_BUS_SEL_GPLL, PERI_ACLK_DIV_MSK, PERI_ACLK_DIV_SHIFT, PERI_ACLK_HZ, PERI_HCLK_DIV_MSK, PERI_HCLK_DIV_SHIFT, PERI_HCLK_HZ, PERI_PCLK_DIV_MSK, PERI_PCLK_DIV_SHIFT, PERI_PCLK_HZ, PERI_SEL_GPLL, PERIHP_ACLK_HZ, PERIHP_HCLK_HZ, PERIHP_PCLK_HZ, PERILP0_ACLK_HZ, PERILP0_HCLK_HZ, PERILP0_PCLK_HZ, PERILP1_HCLK_HZ, PERILP1_PCLK_HZ, PMU_PCLK_DIV_CON_MASK, PMU_PCLK_DIV_CON_SHIFT, PMU_PCLK_HZ, rk3399_pmucru_reg::pmucru_clksel, pmucru_ptr, rk3399_pmucru_reg::ppll_con, PPLL_HZ, ppll_init_cfg, read32(), rk3288_grf, RK_CLRSETBITS, RK_SETBITS, rkclk_set_pll(), rk3288_grf_regs::soc_status, SOCSTS_CPLL_LOCK, SOCSTS_GPLL_LOCK, udelay(), and write32().

Referenced by bootblock_soc_init().

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◆ rkclk_was_watchdog_reset()

int rkclk_was_watchdog_reset ( void  )

Definition at line 652 of file clock.c.

References rk3288_cru_reg::cru_glb_rst_st, cru_ptr, and read32().

Referenced by bootblock_mainboard_init().

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Variable Documentation

◆ cru_ptr

struct rk3399_cru_reg* const cru_ptr = (void *)CRU_BASE
static

Definition at line 60 of file clock.h.

◆ pmucru_ptr

struct rk3399_pmucru_reg* const pmucru_ptr = (void *)PMUCRU_BASE
static

Definition at line 59 of file clock.h.

Referenced by dram_all_config(), rkclk_configure_spi(), rkclk_i2c_clock_for_bus(), and rkclk_init().