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pll.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 /*
4  * This file is created based on MT8186 Functional Specification
5  * Chapter number: 3.2
6  */
7 
8 #ifndef SOC_MEDIATEK_MT8186_PLL_H
9 #define SOC_MEDIATEK_MT8186_PLL_H
10 
11 #include <device/mmio.h>
12 #include <types.h>
13 #include <soc/pll_common.h>
14 
15 struct mtk_topckgen_regs {
16  u32 clk_mode;
17  u32 clk_cfg_update;
18  u32 clk_cfg_update1;
19  u32 reserved1[13];
20  u32 clk_cfg_0;
21  u32 clk_cfg_0_set;
22  u32 clk_cfg_0_clr;
23  u32 reserved2[1];
24  u32 clk_cfg_1;
25  u32 clk_cfg_1_set;
26  u32 clk_cfg_1_clr;
27  u32 reserved3[1];
28  u32 clk_cfg_2;
29  u32 clk_cfg_2_set;
30  u32 clk_cfg_2_clr;
31  u32 reserved4[1];
32  u32 clk_cfg_3;
33  u32 clk_cfg_3_set;
34  u32 clk_cfg_3_clr;
35  u32 reserved5[1];
36  u32 clk_cfg_4;
37  u32 clk_cfg_4_set;
38  u32 clk_cfg_4_clr;
39  u32 reserved6[1];
40  u32 clk_cfg_5;
41  u32 clk_cfg_5_set;
42  u32 clk_cfg_5_clr;
43  u32 reserved7[1];
44  u32 clk_cfg_6;
45  u32 clk_cfg_6_set;
46  u32 clk_cfg_6_clr;
47  u32 reserved8[1];
48  u32 clk_cfg_7;
49  u32 clk_cfg_7_set;
50  u32 clk_cfg_7_clr;
51  u32 reserved9[1];
52  u32 clk_cfg_8;
53  u32 clk_cfg_8_set;
54  u32 clk_cfg_8_clr;
55  u32 reserved10[1];
56  u32 clk_cfg_9;
57  u32 clk_cfg_9_set;
58  u32 clk_cfg_9_clr;
59  u32 reserved11[1];
60  u32 clk_cfg_10;
61  u32 clk_cfg_10_set;
62  u32 clk_cfg_10_clr;
63  u32 clk_cfg_11;
64  u32 clk_cfg_11_set;
65  u32 clk_cfg_11_clr;
66  u32 reserved12[2];
67  u32 clk_cfg_12;
68  u32 clk_cfg_12_set;
69  u32 clk_cfg_12_clr;
70  u32 reserved13[1];
71  u32 clk_cfg_13;
72  u32 clk_cfg_13_set;
73  u32 clk_cfg_13_clr;
74  u32 reserved14[1];
75  u32 clk_cfg_14;
76  u32 clk_cfg_14_set;
77  u32 clk_cfg_14_clr;
78  u32 reserved15[1];
79  u32 clk_cfg_20;
80  u32 clk_cfg_20_set;
81  u32 clk_cfg_20_clr;
82  u32 reserved16[1];
83  u32 clk_misc_cfg_0;
84  u32 reserved17[3];
85  u32 clk_misc_cfg_1;
86  u32 reserved18[10];
87  u32 clk_dbg_cfg;
88  u32 clk_cfg_15;
89  u32 clk_cfg_15_set;
90  u32 clk_cfg_15_clr;
91  u32 reserved19[29];
92  u32 clk_scp_cfg_0;
93  u32 reserved20[3];
94  u32 clk_scp_cfg_1;
95  u32 reserved21[3];
96  u32 clk26cali_0;
97  u32 clk26cali_1;
98  u32 reserved22[2];
99  u32 cksta_reg;
100  u32 cksta_reg1;
101  u32 reserved23[50];
102  u32 clkmon_clk_sel_reg;
103  u32 clkmon_k1_reg;
104  u32 reserved24[6];
105  u32 clk_auddiv_0;
106  u32 clk_auddiv_1;
107  u32 clk_auddiv_2;
108  u32 aud_top_cfg;
109  u32 aud_top_mon;
110  u32 clk_auddiv_3;
111  u32 reserved25[1];
112  u32 usb_top_cfg;
113  u32 reserved26[112];
114  u32 clk_extck_reg;
115 };
116 
117 check_member(mtk_topckgen_regs, clk_mode, 0x0);
118 check_member(mtk_topckgen_regs, clk_cfg_update, 0x4);
119 check_member(mtk_topckgen_regs, clk_cfg_update1, 0x8);
120 check_member(mtk_topckgen_regs, clk_cfg_0, 0x40);
121 check_member(mtk_topckgen_regs, clk_cfg_0_set, 0x44);
122 check_member(mtk_topckgen_regs, clk_cfg_0_clr, 0x48);
123 check_member(mtk_topckgen_regs, clk_cfg_1, 0x50);
124 check_member(mtk_topckgen_regs, clk_cfg_1_set, 0x54);
125 check_member(mtk_topckgen_regs, clk_cfg_1_clr, 0x58);
126 check_member(mtk_topckgen_regs, clk_cfg_2, 0x60);
127 check_member(mtk_topckgen_regs, clk_cfg_2_set, 0x64);
128 check_member(mtk_topckgen_regs, clk_cfg_2_clr, 0x68);
129 check_member(mtk_topckgen_regs, clk_cfg_3, 0x70);
130 check_member(mtk_topckgen_regs, clk_cfg_3_set, 0x74);
131 check_member(mtk_topckgen_regs, clk_cfg_3_clr, 0x78);
132 check_member(mtk_topckgen_regs, clk_cfg_4, 0x80);
133 check_member(mtk_topckgen_regs, clk_cfg_4_set, 0x84);
134 check_member(mtk_topckgen_regs, clk_cfg_4_clr, 0x88);
135 check_member(mtk_topckgen_regs, clk_cfg_5, 0x90);
136 check_member(mtk_topckgen_regs, clk_cfg_5_set, 0x94);
137 check_member(mtk_topckgen_regs, clk_cfg_5_clr, 0x98);
138 check_member(mtk_topckgen_regs, clk_cfg_6, 0xa0);
139 check_member(mtk_topckgen_regs, clk_cfg_6_set, 0xa4);
140 check_member(mtk_topckgen_regs, clk_cfg_6_clr, 0xa8);
141 check_member(mtk_topckgen_regs, clk_cfg_7, 0xb0);
142 check_member(mtk_topckgen_regs, clk_cfg_7_set, 0xb4);
143 check_member(mtk_topckgen_regs, clk_cfg_7_clr, 0xb8);
144 check_member(mtk_topckgen_regs, clk_cfg_8, 0xc0);
145 check_member(mtk_topckgen_regs, clk_cfg_8_set, 0xc4);
146 check_member(mtk_topckgen_regs, clk_cfg_8_clr, 0xc8);
147 check_member(mtk_topckgen_regs, clk_cfg_9, 0xd0);
148 check_member(mtk_topckgen_regs, clk_cfg_9_set, 0xd4);
149 check_member(mtk_topckgen_regs, clk_cfg_9_clr, 0xd8);
150 check_member(mtk_topckgen_regs, clk_cfg_10, 0xe0);
151 check_member(mtk_topckgen_regs, clk_cfg_10_set, 0xe4);
152 check_member(mtk_topckgen_regs, clk_cfg_10_clr, 0xe8);
153 check_member(mtk_topckgen_regs, clk_cfg_11, 0xec);
154 check_member(mtk_topckgen_regs, clk_cfg_11_set, 0xf0);
155 check_member(mtk_topckgen_regs, clk_cfg_11_clr, 0xf4);
156 check_member(mtk_topckgen_regs, clk_cfg_12, 0x100);
157 check_member(mtk_topckgen_regs, clk_cfg_12_set, 0x104);
158 check_member(mtk_topckgen_regs, clk_cfg_12_clr, 0x108);
159 check_member(mtk_topckgen_regs, clk_cfg_13, 0x110);
160 check_member(mtk_topckgen_regs, clk_cfg_13_set, 0x114);
161 check_member(mtk_topckgen_regs, clk_cfg_13_clr, 0x118);
162 check_member(mtk_topckgen_regs, clk_cfg_14, 0x120);
163 check_member(mtk_topckgen_regs, clk_cfg_14_set, 0x124);
164 check_member(mtk_topckgen_regs, clk_cfg_14_clr, 0x128);
165 check_member(mtk_topckgen_regs, clk_cfg_20, 0x130);
166 check_member(mtk_topckgen_regs, clk_cfg_20_set, 0x134);
167 check_member(mtk_topckgen_regs, clk_cfg_20_clr, 0x138);
168 check_member(mtk_topckgen_regs, clk_misc_cfg_0, 0x140);
169 check_member(mtk_topckgen_regs, clk_misc_cfg_1, 0x150);
170 check_member(mtk_topckgen_regs, clk_dbg_cfg, 0x17c);
171 check_member(mtk_topckgen_regs, clk_cfg_15, 0x180);
172 check_member(mtk_topckgen_regs, clk_cfg_15_set, 0x184);
173 check_member(mtk_topckgen_regs, clk_cfg_15_clr, 0x188);
174 check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x200);
175 check_member(mtk_topckgen_regs, clk_scp_cfg_1, 0x210);
176 check_member(mtk_topckgen_regs, clk26cali_0, 0x220);
177 check_member(mtk_topckgen_regs, clk26cali_1, 0x224);
178 check_member(mtk_topckgen_regs, cksta_reg, 0x230);
179 check_member(mtk_topckgen_regs, cksta_reg1, 0x234);
180 check_member(mtk_topckgen_regs, clkmon_clk_sel_reg, 0x300);
181 check_member(mtk_topckgen_regs, clkmon_k1_reg, 0x304);
182 check_member(mtk_topckgen_regs, clk_auddiv_0, 0x320);
183 check_member(mtk_topckgen_regs, clk_auddiv_1, 0x324);
184 check_member(mtk_topckgen_regs, clk_auddiv_2, 0x328);
185 check_member(mtk_topckgen_regs, aud_top_cfg, 0x32c);
186 check_member(mtk_topckgen_regs, aud_top_mon, 0x330);
187 check_member(mtk_topckgen_regs, clk_auddiv_3, 0x334);
188 check_member(mtk_topckgen_regs, usb_top_cfg, 0x33c);
189 check_member(mtk_topckgen_regs, clk_extck_reg, 0x500);
190 
191 struct mtk_apmixed_regs {
192  u32 ap_pll_con0;
193  u32 ap_pll_con1;
194  u32 ap_pll_con2;
195  u32 ap_pll_con3;
196  u32 ap_pll_con4;
197  u32 ap_pll_con5;
198  u32 clksq_stb_con0;
199  u32 pll_pwr_con0;
200  u32 pll_pwr_con1;
201  u32 pll_iso_con0;
202  u32 pll_iso_con1;
203  u32 pll_stb_con0;
204  u32 div_stb_con0;
205  u32 pll_chg_con0;
206  u32 pll_test_con0;
207  u32 pll_test_con1;
208  u32 apll1_tuner_con0;
209  u32 apll2_tuner_con0;
210  u32 reserved1[2];
211  u32 pllon_con0;
212  u32 pllon_con1;
213  u32 reserved2[106];
214  u32 ap_pllgp1_con0;
215  u32 armpll_ll_con0;
216  u32 armpll_ll_con1;
217  u32 armpll_ll_con2;
218  u32 armpll_ll_con3;
219  u32 armpll_bl_con0;
220  u32 armpll_bl_con1;
221  u32 armpll_bl_con2;
222  u32 armpll_bl_con3;
223  u32 ccipll_con0;
224  u32 ccipll_con1;
225  u32 ccipll_con2;
226  u32 ccipll_con3;
227  u32 apupll_con0;
228  u32 apupll_con1;
229  u32 apupll_con2;
230  u32 apupll_con3;
231  u32 mainpll_con0;
232  u32 mainpll_con1;
233  u32 mainpll_con2;
234  u32 mainpll_con3;
235  u32 mmpll_con0;
236  u32 mmpll_con1;
237  u32 mmpll_con2;
238  u32 mmpll_con3;
239  u32 tvdpll_con0;
240  u32 tvdpll_con1;
241  u32 tvdpll_con2;
242  u32 tvdpll_con3;
243  u32 mpll_con0;
244  u32 mpll_con1;
245  u32 mpll_con2;
246  u32 mpll_con3;
247  u32 reserved3[31];
248  u32 ap_pllgp2_con0;
249  u32 adsppll_con0;
250  u32 adsppll_con1;
251  u32 adsppll_con2;
252  u32 adsppll_con3;
253  u32 mfgpll_con0;
254  u32 mfgpll_con1;
255  u32 mfgpll_con2;
256  u32 mfgpll_con3;
257  u32 univpll_con0;
258  u32 univpll_con1;
259  u32 univpll_con2;
260  u32 univpll_con3;
261  u32 apll1_con0;
262  u32 apll1_con1;
263  u32 apll1_con2;
264  u32 apll1_con3;
265  u32 apll1_con4;
266  u32 apll2_con0;
267  u32 apll2_con1;
268  u32 apll2_con2;
269  u32 apll2_con3;
270  u32 apll2_con4;
271  u32 nnapll_con0;
272  u32 nnapll_con1;
273  u32 nnapll_con2;
274  u32 nnapll_con3;
275  u32 nna2pll_con0;
276  u32 nna2pll_con1;
277  u32 nna2pll_con2;
278  u32 nna2pll_con3;
279  u32 mdbrppll_con0;
280  u32 mdbrppll_con1;
281  u32 mdbrppll_con2;
282  u32 mdbrppll_con3;
283  u32 msdcpll_con0;
284  u32 msdcpll_con1;
285  u32 msdcpll_con2;
286  u32 msdcpll_con3;
287  u32 mdbpipll_con0;
288  u32 mdbpipll_con1;
289  u32 mdbpipll_con2;
290  u32 mdbpipll_con3;
291  u32 reserved4[21];
292  u32 ap_auxadc_con0;
293  u32 ap_auxadc_con1;
294  u32 reserved5[30];
295  u32 ap_tsense_con0;
296  u32 ap_tsense_con1;
297  u32 ap_tsense_con2;
298  u32 reserved6[29];
299  u32 ulposc_con0;
300  u32 ulposc_con1;
301  u32 reserved7[30];
302  u32 ulposc2_con0;
303  u32 ulposc2_con1;
304  u32 reserved8[158];
305  u32 ap_abist_mon_con0;
306  u32 ap_abist_mon_con1;
307  u32 ap_abist_mon_con2;
308  u32 ap_abist_mon_con3;
309  u32 occscan_con0;
310  u32 clkdiv_con0;
311  u32 occscan_con1;
312  u32 occscan_con2;
313  u32 occscan_con3;
314  u32 mcu_occscan_con0;
315  u32 occscan_con4;
316  u32 occscan_con5;
317  u32 reserved9[52];
318  u32 rsv_rw0_con0;
319  u32 rsv_rw1_con0;
320  u32 rsv_ro_con0;
321 };
322 check_member(mtk_apmixed_regs, ap_pll_con0, 0x0);
323 check_member(mtk_apmixed_regs, ap_pll_con1, 0x4);
324 check_member(mtk_apmixed_regs, ap_pll_con2, 0x8);
325 check_member(mtk_apmixed_regs, ap_pll_con3, 0xc);
326 check_member(mtk_apmixed_regs, ap_pll_con4, 0x10);
327 check_member(mtk_apmixed_regs, ap_pll_con5, 0x14);
328 check_member(mtk_apmixed_regs, clksq_stb_con0, 0x18);
329 check_member(mtk_apmixed_regs, pll_pwr_con0, 0x1c);
330 check_member(mtk_apmixed_regs, pll_pwr_con1, 0x20);
331 check_member(mtk_apmixed_regs, pll_iso_con0, 0x24);
332 check_member(mtk_apmixed_regs, pll_iso_con1, 0x28);
333 check_member(mtk_apmixed_regs, pll_stb_con0, 0x2c);
334 check_member(mtk_apmixed_regs, div_stb_con0, 0x30);
335 check_member(mtk_apmixed_regs, pll_chg_con0, 0x34);
336 check_member(mtk_apmixed_regs, pll_test_con0, 0x38);
337 check_member(mtk_apmixed_regs, pll_test_con1, 0x3c);
338 check_member(mtk_apmixed_regs, apll1_tuner_con0, 0x40);
339 check_member(mtk_apmixed_regs, apll2_tuner_con0, 0x44);
340 check_member(mtk_apmixed_regs, pllon_con0, 0x50);
341 check_member(mtk_apmixed_regs, pllon_con1, 0x54);
342 check_member(mtk_apmixed_regs, ap_pllgp1_con0, 0x200);
343 check_member(mtk_apmixed_regs, armpll_ll_con0, 0x204);
344 check_member(mtk_apmixed_regs, armpll_ll_con1, 0x208);
345 check_member(mtk_apmixed_regs, armpll_ll_con2, 0x20c);
346 check_member(mtk_apmixed_regs, armpll_ll_con3, 0x210);
347 check_member(mtk_apmixed_regs, armpll_bl_con0, 0x214);
348 check_member(mtk_apmixed_regs, armpll_bl_con1, 0x218);
349 check_member(mtk_apmixed_regs, armpll_bl_con2, 0x21c);
350 check_member(mtk_apmixed_regs, armpll_bl_con3, 0x220);
351 check_member(mtk_apmixed_regs, ccipll_con0, 0x224);
352 check_member(mtk_apmixed_regs, ccipll_con1, 0x228);
353 check_member(mtk_apmixed_regs, ccipll_con2, 0x22c);
354 check_member(mtk_apmixed_regs, ccipll_con3, 0x230);
355 check_member(mtk_apmixed_regs, apupll_con0, 0x234);
356 check_member(mtk_apmixed_regs, apupll_con1, 0x238);
357 check_member(mtk_apmixed_regs, apupll_con2, 0x23c);
358 check_member(mtk_apmixed_regs, apupll_con3, 0x240);
359 check_member(mtk_apmixed_regs, mainpll_con0, 0x244);
360 check_member(mtk_apmixed_regs, mainpll_con1, 0x248);
361 check_member(mtk_apmixed_regs, mainpll_con2, 0x24c);
362 check_member(mtk_apmixed_regs, mainpll_con3, 0x250);
363 check_member(mtk_apmixed_regs, mmpll_con0, 0x254);
364 check_member(mtk_apmixed_regs, mmpll_con1, 0x258);
365 check_member(mtk_apmixed_regs, mmpll_con2, 0x25c);
366 check_member(mtk_apmixed_regs, mmpll_con3, 0x260);
367 check_member(mtk_apmixed_regs, tvdpll_con0, 0x264);
368 check_member(mtk_apmixed_regs, tvdpll_con1, 0x268);
369 check_member(mtk_apmixed_regs, tvdpll_con2, 0x26c);
370 check_member(mtk_apmixed_regs, tvdpll_con3, 0x270);
371 check_member(mtk_apmixed_regs, mpll_con0, 0x274);
372 check_member(mtk_apmixed_regs, mpll_con1, 0x278);
373 check_member(mtk_apmixed_regs, mpll_con2, 0x27c);
374 check_member(mtk_apmixed_regs, mpll_con3, 0x280);
375 check_member(mtk_apmixed_regs, ap_pllgp2_con0, 0x300);
376 check_member(mtk_apmixed_regs, adsppll_con0, 0x304);
377 check_member(mtk_apmixed_regs, adsppll_con1, 0x308);
378 check_member(mtk_apmixed_regs, adsppll_con2, 0x30c);
379 check_member(mtk_apmixed_regs, adsppll_con3, 0x310);
380 check_member(mtk_apmixed_regs, mfgpll_con0, 0x314);
381 check_member(mtk_apmixed_regs, mfgpll_con1, 0x318);
382 check_member(mtk_apmixed_regs, mfgpll_con2, 0x31c);
383 check_member(mtk_apmixed_regs, mfgpll_con3, 0x320);
384 check_member(mtk_apmixed_regs, univpll_con0, 0x324);
385 check_member(mtk_apmixed_regs, univpll_con1, 0x328);
386 check_member(mtk_apmixed_regs, univpll_con2, 0x32c);
387 check_member(mtk_apmixed_regs, univpll_con3, 0x330);
388 check_member(mtk_apmixed_regs, apll1_con0, 0x334);
389 check_member(mtk_apmixed_regs, apll1_con1, 0x338);
390 check_member(mtk_apmixed_regs, apll1_con2, 0x33c);
391 check_member(mtk_apmixed_regs, apll1_con3, 0x340);
392 check_member(mtk_apmixed_regs, apll1_con4, 0x344);
393 check_member(mtk_apmixed_regs, apll2_con0, 0x348);
394 check_member(mtk_apmixed_regs, apll2_con1, 0x34c);
395 check_member(mtk_apmixed_regs, apll2_con2, 0x350);
396 check_member(mtk_apmixed_regs, apll2_con3, 0x354);
397 check_member(mtk_apmixed_regs, apll2_con4, 0x358);
398 check_member(mtk_apmixed_regs, nnapll_con0, 0x35c);
399 check_member(mtk_apmixed_regs, nnapll_con1, 0x360);
400 check_member(mtk_apmixed_regs, nnapll_con2, 0x364);
401 check_member(mtk_apmixed_regs, nnapll_con3, 0x368);
402 check_member(mtk_apmixed_regs, nna2pll_con0, 0x36c);
403 check_member(mtk_apmixed_regs, nna2pll_con1, 0x370);
404 check_member(mtk_apmixed_regs, nna2pll_con2, 0x374);
405 check_member(mtk_apmixed_regs, nna2pll_con3, 0x378);
406 check_member(mtk_apmixed_regs, mdbrppll_con0, 0x37c);
407 check_member(mtk_apmixed_regs, mdbrppll_con1, 0x380);
408 check_member(mtk_apmixed_regs, mdbrppll_con2, 0x384);
409 check_member(mtk_apmixed_regs, mdbrppll_con3, 0x388);
410 check_member(mtk_apmixed_regs, msdcpll_con0, 0x38c);
411 check_member(mtk_apmixed_regs, msdcpll_con1, 0x390);
412 check_member(mtk_apmixed_regs, msdcpll_con2, 0x394);
413 check_member(mtk_apmixed_regs, msdcpll_con3, 0x398);
414 check_member(mtk_apmixed_regs, mdbpipll_con0, 0x39c);
415 check_member(mtk_apmixed_regs, mdbpipll_con1, 0x3a0);
416 check_member(mtk_apmixed_regs, mdbpipll_con2, 0x3a4);
417 check_member(mtk_apmixed_regs, mdbpipll_con3, 0x3a8);
418 check_member(mtk_apmixed_regs, ap_auxadc_con0, 0x400);
419 check_member(mtk_apmixed_regs, ap_auxadc_con1, 0x404);
420 check_member(mtk_apmixed_regs, ap_tsense_con0, 0x480);
421 check_member(mtk_apmixed_regs, ap_tsense_con1, 0x484);
422 check_member(mtk_apmixed_regs, ap_tsense_con2, 0x488);
423 check_member(mtk_apmixed_regs, ulposc_con0, 0x500);
424 check_member(mtk_apmixed_regs, ulposc_con1, 0x504);
425 check_member(mtk_apmixed_regs, ulposc2_con0, 0x580);
426 check_member(mtk_apmixed_regs, ulposc2_con1, 0x584);
427 check_member(mtk_apmixed_regs, ap_abist_mon_con0, 0x800);
428 check_member(mtk_apmixed_regs, ap_abist_mon_con1, 0x804);
429 check_member(mtk_apmixed_regs, ap_abist_mon_con2, 0x808);
430 check_member(mtk_apmixed_regs, ap_abist_mon_con3, 0x80c);
431 check_member(mtk_apmixed_regs, occscan_con0, 0x810);
432 check_member(mtk_apmixed_regs, clkdiv_con0, 0x814);
433 check_member(mtk_apmixed_regs, occscan_con1, 0x818);
434 check_member(mtk_apmixed_regs, occscan_con2, 0x81c);
435 check_member(mtk_apmixed_regs, occscan_con3, 0x820);
436 check_member(mtk_apmixed_regs, mcu_occscan_con0, 0x824);
437 check_member(mtk_apmixed_regs, occscan_con4, 0x828);
438 check_member(mtk_apmixed_regs, occscan_con5, 0x82c);
439 check_member(mtk_apmixed_regs, rsv_rw0_con0, 0x900);
440 check_member(mtk_apmixed_regs, rsv_rw1_con0, 0x904);
441 check_member(mtk_apmixed_regs, rsv_ro_con0, 0x908);
442 
443 enum {
444  PLL_CKSQ_ON_DELAY = 100,
445  PLL_PWR_ON_DELAY = 30,
446  PLL_ISO_DELAY = 1,
447  PLL_EN_DELAY = 20,
448 };
449 
450 enum {
451  PCW_INTEGER_BITS = 8,
452 };
453 
454 enum {
455  MT8186_PLL_EN = 0x1 << 0,
456  GLITCH_FREE_EN = 0x1 << 4,
457  PLL_DIV_EN = 0xff << 24,
458 };
459 
460 enum {
461  ARMPLL_DIVIDER_PLL1_EN = 0x1 << 4,
462  ARMPLL_DIVIDER_PLL2_EN = 0x1 << 5,
463 };
464 
465 enum {
466  MCU_DIV_MASK = 0x1f << 17,
467  MCU_DIV_1 = 0x8 << 17,
468 
469  MCU_MUX_MASK = 0x3 << 9,
470  MCU_MUX_SRC_PLL = 0x1 << 9,
471  MCU_MUX_SRC_26M = 0x0 << 9,
472 };
473 
474 /* PLL rate */
475 enum {
476  ARMPLL_LL_HZ = 1280 * MHz,
477  ARMPLL_BL_HZ = 1085 * MHz,
478  CCIPLL_HZ = 800 * MHz,
479  MAINPLL_HZ = 1092 * MHz,
480  UNIV2PLL_HZ = 2496UL * MHz,
481  MSDCPLL_HZ = 384 * MHz,
482  MMPLL_HZ = 560 * MHz,
483  NNAPLL_HZ = 800 * MHz,
484  NNA2PLL_HZ = 800 * MHz,
485  ADSPPLL_HZ = 800 * MHz,
486  MFGPLL_HZ = 250 * MHz,
487  TVDPLL_HZ = 297 * MHz,
488  APLL1_HZ = 180633600,
489  APLL2_HZ = 196608 * KHz,
490 };
491 
492 /* top_div rate */
493 enum {
494  CLK26M_HZ = 26 * MHz,
495  MAINPLL_D5_HZ = MAINPLL_HZ / 5,
496 };
497 
498 /* top_mux rate */
499 enum {
500  SPI_HZ = MAINPLL_D5_HZ,
501  UART_HZ = CLK26M_HZ,
502 };
503 
504 DEFINE_BITFIELD(CLK_DBG_CFG_ABIST_CK_SEL, 21, 16)
505 DEFINE_BITFIELD(CLK_DBG_CFG_CKGEN_CK_SEL, 13, 8)
506 DEFINE_BITFIELD(CLK_DBG_CFG_METER_CK_SEL, 1, 0)
507 DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24)
508 DEFINE_BITFIELD(CLK26CALI_0_ENABLE, 12, 12)
509 DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4)
510 
511 DEFINE_BIT(INFRACFG_AO_AUDIO_BUS_REG0, 29)
512 DEFINE_BIT(INFRACFG_AO_ICUSB_BUS_REG0, 28)
513 
514 DEFINE_BITFIELD(INFRACFG_AO_INFRA_BUS_REG0_0, 14, 0)
515 DEFINE_BITFIELD(INFRACFG_AO_INFRA_BUS_REG0_1, 23, 20)
516 DEFINE_BIT(INFRACFG_AO_INFRA_BUS_REG0_2, 30)
517 
518 DEFINE_BIT(INFRACFG_AO_P2P_RX_CLK_REG0_MASK_0, 0)
519 DEFINE_BIT(INFRACFG_AO_P2P_RX_CLK_REG0_MASK_1, 5)
520 
521 DEFINE_BITFIELD(INFRACFG_AO_PERI_BUS_REG0_0, 1, 0)
522 DEFINE_BITFIELD(INFRACFG_AO_PERI_BUS_REG0_1, 27, 3)
523 DEFINE_BIT(INFRACFG_AO_PERI_BUS_REG0_2, 31)
524 
525 #endif /* SOC_MEDIATEK_MT8186_PLL_H */
MHz
#define MHz
Definition: helpers.h:80
KHz
#define KHz
Definition: helpers.h:79
DEFINE_BITFIELD
#define DEFINE_BITFIELD(name, high_bit, low_bit)
Definition: mmio.h:124
DEFINE_BIT
#define DEFINE_BIT(name, bit)
Definition: mmio.h:131
MSDCPLL_HZ
@ MSDCPLL_HZ
Definition: pll.h:198
MAINPLL_HZ
@ MAINPLL_HZ
Definition: pll.h:195
MMPLL_HZ
@ MMPLL_HZ
Definition: pll.h:197
APLL1_HZ
@ APLL1_HZ
Definition: pll.h:205
APLL2_HZ
@ APLL2_HZ
Definition: pll.h:206
TVDPLL_HZ
@ TVDPLL_HZ
Definition: pll.h:200
UART_HZ
@ UART_HZ
Definition: pll.h:247
SPI_HZ
@ SPI_HZ
Definition: pll.h:248
CLK26M_HZ
@ CLK26M_HZ
Definition: pll.h:215
PLL_ISO_DELAY
@ PLL_ISO_DELAY
Definition: pll.h:183
PLL_EN_DELAY
@ PLL_EN_DELAY
Definition: pll.h:184
PLL_PWR_ON_DELAY
@ PLL_PWR_ON_DELAY
Definition: pll.h:182
check_member
check_member(mtk_topckgen_regs, clk_cfg_0, 0x40)
PCW_INTEGER_BITS
@ PCW_INTEGER_BITS
Definition: pll.h:188
CCIPLL_HZ
@ CCIPLL_HZ
Definition: pll.h:237
MFGPLL_HZ
@ MFGPLL_HZ
Definition: pll.h:242
ARMPLL_LL_HZ
@ ARMPLL_LL_HZ
Definition: pll.h:235
MAINPLL_D5_HZ
@ MAINPLL_D5_HZ
Definition: pll.h:252
ARMPLL_DIVIDER_PLL1_EN
@ ARMPLL_DIVIDER_PLL1_EN
Definition: pll.h:461
ARMPLL_DIVIDER_PLL2_EN
@ ARMPLL_DIVIDER_PLL2_EN
Definition: pll.h:462
NNAPLL_HZ
@ NNAPLL_HZ
Definition: pll.h:483
ARMPLL_BL_HZ
@ ARMPLL_BL_HZ
Definition: pll.h:477
UNIV2PLL_HZ
@ UNIV2PLL_HZ
Definition: pll.h:480
ADSPPLL_HZ
@ ADSPPLL_HZ
Definition: pll.h:485
NNA2PLL_HZ
@ NNA2PLL_HZ
Definition: pll.h:484
PLL_CKSQ_ON_DELAY
@ PLL_CKSQ_ON_DELAY
Definition: pll.h:444
GLITCH_FREE_EN
@ GLITCH_FREE_EN
Definition: pll.h:456
MT8186_PLL_EN
@ MT8186_PLL_EN
Definition: pll.h:455
PLL_DIV_EN
@ PLL_DIV_EN
Definition: pll.h:457
MCU_MUX_MASK
@ MCU_MUX_MASK
Definition: pll.h:469
MCU_DIV_MASK
@ MCU_DIV_MASK
Definition: pll.h:466
MCU_DIV_1
@ MCU_DIV_1
Definition: pll.h:467
MCU_MUX_SRC_PLL
@ MCU_MUX_SRC_PLL
Definition: pll.h:470
MCU_MUX_SRC_26M
@ MCU_MUX_SRC_26M
Definition: pll.h:471
pll_common.h
u32
uint32_t u32
Definition: stdint.h:51
mtk_apmixed_regs
Definition: pll.h:92
mtk_apmixed_regs::msdcpll_con2
u32 msdcpll_con2
Definition: pll.h:134
mtk_apmixed_regs::reserved3
u32 reserved3[2]
Definition: pll.h:162
mtk_apmixed_regs::mcu_occscan_con0
u32 mcu_occscan_con0
Definition: pll.h:198
mtk_apmixed_regs::reserved8
u32 reserved8[158]
Definition: pll.h:304
mtk_apmixed_regs::apupll_con3
u32 apupll_con3
Definition: pll.h:230
mtk_apmixed_regs::pll_test_con0
u32 pll_test_con0
Definition: pll.h:109
mtk_apmixed_regs::apll2_con0
u32 apll2_con0
Definition: pll.h:157
mtk_apmixed_regs::clkdiv_con0
u32 clkdiv_con0
Definition: pll.h:195
mtk_apmixed_regs::ccipll_con3
u32 ccipll_con3
Definition: pll.h:226
mtk_apmixed_regs::ap_pll_con5
u32 ap_pll_con5
Definition: pll.h:98
mtk_apmixed_regs::ap_pllgp2_con0
u32 ap_pllgp2_con0
Definition: pll.h:248
mtk_apmixed_regs::msdcpll_con0
u32 msdcpll_con0
Definition: pll.h:132
mtk_apmixed_regs::armpll_ll_con1
u32 armpll_ll_con1
Definition: pll.h:124
mtk_apmixed_regs::ulposc2_con0
u32 ulposc2_con0
Definition: pll.h:187
mtk_apmixed_regs::mdbpipll_con0
u32 mdbpipll_con0
Definition: pll.h:287
mtk_apmixed_regs::pll_test_con1
u32 pll_test_con1
Definition: pll.h:110
mtk_apmixed_regs::ap_pll_con1
u32 ap_pll_con1
Definition: pll.h:104
mtk_apmixed_regs::tvdpll_con0
u32 tvdpll_con0
Definition: pll.h:140
mtk_apmixed_regs::rsv_ro_con0
u32 rsv_ro_con0
Definition: pll.h:202
mtk_apmixed_regs::apll1_tuner_con0
u32 apll1_tuner_con0
Definition: pll.h:208
mtk_apmixed_regs::occscan_con3
u32 occscan_con3
Definition: pll.h:313
mtk_apmixed_regs::pll_iso_con0
u32 pll_iso_con0
Definition: pll.h:104
mtk_apmixed_regs::reserved1
u32 reserved1[1]
Definition: pll.h:94
mtk_apmixed_regs::adsppll_con1
u32 adsppll_con1
Definition: pll.h:250
mtk_apmixed_regs::apll2_con4
u32 apll2_con4
Definition: pll.h:270
mtk_apmixed_regs::mainpll_con0
u32 mainpll_con0
Definition: pll.h:120
mtk_apmixed_regs::apll2_con1
u32 apll2_con1
Definition: pll.h:158
mtk_apmixed_regs::mfgpll_con0
u32 mfgpll_con0
Definition: pll.h:139
mtk_apmixed_regs::reserved5
u32 reserved5[60]
Definition: pll.h:189
mtk_apmixed_regs::apll1_con2
u32 apll1_con2
Definition: pll.h:154
mtk_apmixed_regs::mmpll_con3
u32 mmpll_con3
Definition: pll.h:238
mtk_apmixed_regs::occscan_con5
u32 occscan_con5
Definition: pll.h:316
mtk_apmixed_regs::nnapll_con3
u32 nnapll_con3
Definition: pll.h:274
mtk_apmixed_regs::ap_tsense_con1
u32 ap_tsense_con1
Definition: pll.h:296
mtk_apmixed_regs::armpll_ll_con0
u32 armpll_ll_con0
Definition: pll.h:123
mtk_apmixed_regs::mdbrppll_con0
u32 mdbrppll_con0
Definition: pll.h:279
mtk_apmixed_regs::ap_pll_con4
u32 ap_pll_con4
Definition: pll.h:97
mtk_apmixed_regs::mfgpll_con2
u32 mfgpll_con2
Definition: pll.h:141
mtk_apmixed_regs::nna2pll_con0
u32 nna2pll_con0
Definition: pll.h:275
mtk_apmixed_regs::ap_pllgp1_con0
u32 ap_pllgp1_con0
Definition: pll.h:214
mtk_apmixed_regs::ulposc_con0
u32 ulposc_con0
Definition: pll.h:185
mtk_apmixed_regs::nna2pll_con3
u32 nna2pll_con3
Definition: pll.h:278
mtk_apmixed_regs::nnapll_con0
u32 nnapll_con0
Definition: pll.h:271
mtk_apmixed_regs::ap_pll_con0
u32 ap_pll_con0
Definition: pll.h:93
mtk_apmixed_regs::ccipll_con1
u32 ccipll_con1
Definition: pll.h:160
mtk_apmixed_regs::reserved6
u32 reserved6[55]
Definition: pll.h:199
mtk_apmixed_regs::armpll_ll_con3
u32 armpll_ll_con3
Definition: pll.h:218
mtk_apmixed_regs::apupll_con0
u32 apupll_con0
Definition: pll.h:227
mtk_apmixed_regs::pll_chg_con0
u32 pll_chg_con0
Definition: pll.h:108
mtk_apmixed_regs::mdbrppll_con3
u32 mdbrppll_con3
Definition: pll.h:282
mtk_apmixed_regs::apll1_con4
u32 apll1_con4
Definition: pll.h:265
mtk_apmixed_regs::apll2_tuner_con0
u32 apll2_tuner_con0
Definition: pll.h:209
mtk_apmixed_regs::mdbrppll_con1
u32 mdbrppll_con1
Definition: pll.h:280
mtk_apmixed_regs::clksq_stb_con0
u32 clksq_stb_con0
Definition: pll.h:101
mtk_apmixed_regs::armpll_bl_con1
u32 armpll_bl_con1
Definition: pll.h:220
mtk_apmixed_regs::ap_pll_con3
u32 ap_pll_con3
Definition: pll.h:96
mtk_apmixed_regs::ccipll_con2
u32 ccipll_con2
Definition: pll.h:161
mtk_apmixed_regs::mdbrppll_con2
u32 mdbrppll_con2
Definition: pll.h:281
mtk_apmixed_regs::ap_tsense_con0
u32 ap_tsense_con0
Definition: pll.h:295
mtk_apmixed_regs::univpll_con2
u32 univpll_con2
Definition: pll.h:126
mtk_apmixed_regs::mdbpipll_con1
u32 mdbpipll_con1
Definition: pll.h:288
mtk_apmixed_regs::mfgpll_con1
u32 mfgpll_con1
Definition: pll.h:140
mtk_apmixed_regs::ap_auxadc_con1
u32 ap_auxadc_con1
Definition: pll.h:175
mtk_apmixed_regs::nnapll_con2
u32 nnapll_con2
Definition: pll.h:273
mtk_apmixed_regs::ccipll_con0
u32 ccipll_con0
Definition: pll.h:159
mtk_apmixed_regs::reserved9
u32 reserved9[52]
Definition: pll.h:317
mtk_apmixed_regs::apupll_con2
u32 apupll_con2
Definition: pll.h:229
mtk_apmixed_regs::occscan_con1
u32 occscan_con1
Definition: pll.h:196
mtk_apmixed_regs::ap_abist_mon_con3
u32 ap_abist_mon_con3
Definition: pll.h:193
mtk_apmixed_regs::reserved2
u32 reserved2[110]
Definition: pll.h:111
mtk_apmixed_regs::mpll_con2
u32 mpll_con2
Definition: pll.h:146
mtk_apmixed_regs::mdbpipll_con2
u32 mdbpipll_con2
Definition: pll.h:289
mtk_apmixed_regs::mainpll_con2
u32 mainpll_con2
Definition: pll.h:122
mtk_apmixed_regs::armpll_bl_con3
u32 armpll_bl_con3
Definition: pll.h:222
mtk_apmixed_regs::rsv_rw1_con0
u32 rsv_rw1_con0
Definition: pll.h:201
mtk_apmixed_regs::apupll_con1
u32 apupll_con1
Definition: pll.h:228
mtk_apmixed_regs::apll1_con1
u32 apll1_con1
Definition: pll.h:153
mtk_apmixed_regs::univpll_con1
u32 univpll_con1
Definition: pll.h:125
mtk_apmixed_regs::mmpll_con0
u32 mmpll_con0
Definition: pll.h:128
mtk_apmixed_regs::mpll_con1
u32 mpll_con1
Definition: pll.h:145
mtk_apmixed_regs::pll_stb_con0
u32 pll_stb_con0
Definition: pll.h:106
mtk_apmixed_regs::armpll_bl_con0
u32 armpll_bl_con0
Definition: pll.h:219
mtk_apmixed_regs::tvdpll_con2
u32 tvdpll_con2
Definition: pll.h:142
mtk_apmixed_regs::mmpll_con1
u32 mmpll_con1
Definition: pll.h:129
mtk_apmixed_regs::mainpll_con3
u32 mainpll_con3
Definition: pll.h:234
mtk_apmixed_regs::apll2_con3
u32 apll2_con3
Definition: pll.h:160
mtk_apmixed_regs::armpll_bl_con2
u32 armpll_bl_con2
Definition: pll.h:221
mtk_apmixed_regs::univpll_con3
u32 univpll_con3
Definition: pll.h:260
mtk_apmixed_regs::tvdpll_con3
u32 tvdpll_con3
Definition: pll.h:242
mtk_apmixed_regs::nnapll_con1
u32 nnapll_con1
Definition: pll.h:272
mtk_apmixed_regs::tvdpll_con1
u32 tvdpll_con1
Definition: pll.h:141
mtk_apmixed_regs::nna2pll_con1
u32 nna2pll_con1
Definition: pll.h:276
mtk_apmixed_regs::pll_pwr_con0
u32 pll_pwr_con0
Definition: pll.h:102
mtk_apmixed_regs::adsppll_con0
u32 adsppll_con0
Definition: pll.h:249
mtk_apmixed_regs::mmpll_con2
u32 mmpll_con2
Definition: pll.h:130
mtk_apmixed_regs::adsppll_con2
u32 adsppll_con2
Definition: pll.h:251
mtk_apmixed_regs::occscan_con0
u32 occscan_con0
Definition: pll.h:194
mtk_apmixed_regs::apll1_con0
u32 apll1_con0
Definition: pll.h:152
mtk_apmixed_regs::ap_tsense_con2
u32 ap_tsense_con2
Definition: pll.h:297
mtk_apmixed_regs::occscan_con4
u32 occscan_con4
Definition: pll.h:315
mtk_apmixed_regs::reserved7
u32 reserved7[30]
Definition: pll.h:301
mtk_apmixed_regs::pll_iso_con1
u32 pll_iso_con1
Definition: pll.h:105
mtk_apmixed_regs::pllon_con0
u32 pllon_con0
Definition: pll.h:211
mtk_apmixed_regs::ulposc2_con1
u32 ulposc2_con1
Definition: pll.h:188
mtk_apmixed_regs::mainpll_con1
u32 mainpll_con1
Definition: pll.h:121
mtk_apmixed_regs::ulposc_con1
u32 ulposc_con1
Definition: pll.h:186
mtk_apmixed_regs::div_stb_con0
u32 div_stb_con0
Definition: pll.h:107
mtk_apmixed_regs::ap_auxadc_con0
u32 ap_auxadc_con0
Definition: pll.h:174
mtk_apmixed_regs::msdcpll_con1
u32 msdcpll_con1
Definition: pll.h:133
mtk_apmixed_regs::nna2pll_con2
u32 nna2pll_con2
Definition: pll.h:277
mtk_apmixed_regs::mfgpll_con3
u32 mfgpll_con3
Definition: pll.h:256
mtk_apmixed_regs::apll1_con3
u32 apll1_con3
Definition: pll.h:155
mtk_apmixed_regs::reserved4
u32 reserved4[1]
Definition: pll.h:170
mtk_apmixed_regs::ap_abist_mon_con1
u32 ap_abist_mon_con1
Definition: pll.h:191
mtk_apmixed_regs::ap_abist_mon_con0
u32 ap_abist_mon_con0
Definition: pll.h:190
mtk_apmixed_regs::ap_pll_con2
u32 ap_pll_con2
Definition: pll.h:95
mtk_apmixed_regs::apll2_con2
u32 apll2_con2
Definition: pll.h:159
mtk_apmixed_regs::pllon_con1
u32 pllon_con1
Definition: pll.h:212
mtk_apmixed_regs::univpll_con0
u32 univpll_con0
Definition: pll.h:124
mtk_apmixed_regs::adsppll_con3
u32 adsppll_con3
Definition: pll.h:252
mtk_apmixed_regs::mpll_con3
u32 mpll_con3
Definition: pll.h:246
mtk_apmixed_regs::mdbpipll_con3
u32 mdbpipll_con3
Definition: pll.h:290
mtk_apmixed_regs::rsv_rw0_con0
u32 rsv_rw0_con0
Definition: pll.h:200
mtk_apmixed_regs::occscan_con2
u32 occscan_con2
Definition: pll.h:197
mtk_apmixed_regs::msdcpll_con3
u32 msdcpll_con3
Definition: pll.h:286
mtk_apmixed_regs::mpll_con0
u32 mpll_con0
Definition: pll.h:144
mtk_apmixed_regs::armpll_ll_con2
u32 armpll_ll_con2
Definition: pll.h:125
mtk_apmixed_regs::ap_abist_mon_con2
u32 ap_abist_mon_con2
Definition: pll.h:192
mtk_apmixed_regs::pll_pwr_con1
u32 pll_pwr_con1
Definition: pll.h:103
mtk_topckgen_regs
Definition: pll.h:9
mtk_topckgen_regs::clk_extck_reg
u32 clk_extck_reg
Definition: pll.h:83
mtk_topckgen_regs::clk_cfg_13_set
u32 clk_cfg_13_set
Definition: pll.h:54
mtk_topckgen_regs::clk_cfg_2_set
u32 clk_cfg_2_set
Definition: pll.h:26
mtk_topckgen_regs::reserved11
u32 reserved11[1]
Definition: pll.h:52
mtk_topckgen_regs::reserved21
u32 reserved21[3]
Definition: pll.h:95
mtk_topckgen_regs::clk_misc_cfg_1
u32 clk_misc_cfg_1
Definition: pll.h:72
mtk_topckgen_regs::clk_cfg_15_clr
u32 clk_cfg_15_clr
Definition: pll.h:90
mtk_topckgen_regs::reserved23
u32 reserved23[50]
Definition: pll.h:101
mtk_topckgen_regs::clk_cfg_1
u32 clk_cfg_1
Definition: pll.h:21
mtk_topckgen_regs::clk_auddiv_1
u32 clk_auddiv_1
Definition: pll.h:63
mtk_topckgen_regs::clk_cfg_12_set
u32 clk_cfg_12_set
Definition: pll.h:50
mtk_topckgen_regs::reserved19
u32 reserved19[63]
Definition: pll.h:82
mtk_topckgen_regs::clk_cfg_7_set
u32 clk_cfg_7_set
Definition: pll.h:46
mtk_topckgen_regs::clk_cfg_9
u32 clk_cfg_9
Definition: pll.h:58
mtk_topckgen_regs::aud_top_cfg
u32 aud_top_cfg
Definition: pll.h:77
mtk_topckgen_regs::clk_mode
u32 clk_mode
Definition: pll.h:10
mtk_topckgen_regs::reserved26
u32 reserved26[112]
Definition: pll.h:113
mtk_topckgen_regs::clk_cfg_update
u32 clk_cfg_update
Definition: pll.h:11
mtk_topckgen_regs::clk_auddiv_0
u32 clk_auddiv_0
Definition: pll.h:62
mtk_topckgen_regs::clk_cfg_12_clr
u32 clk_cfg_12_clr
Definition: pll.h:51
mtk_topckgen_regs::clk_cfg_11_set
u32 clk_cfg_11_set
Definition: pll.h:64
mtk_topckgen_regs::cksta_reg
u32 cksta_reg
Definition: pll.h:78
mtk_topckgen_regs::reserved22
u32 reserved22[2]
Definition: pll.h:98
mtk_topckgen_regs::clk_cfg_6
u32 clk_cfg_6
Definition: pll.h:41
mtk_topckgen_regs::clk_misc_cfg_0
u32 clk_misc_cfg_0
Definition: pll.h:71
mtk_topckgen_regs::clk_scp_cfg_1
u32 clk_scp_cfg_1
Definition: pll.h:69
mtk_topckgen_regs::clkmon_k1_reg
u32 clkmon_k1_reg
Definition: pll.h:72
mtk_topckgen_regs::reserved25
u32 reserved25[1]
Definition: pll.h:111
mtk_topckgen_regs::reserved13
u32 reserved13[4]
Definition: pll.h:61
mtk_topckgen_regs::clk_cfg_9_set
u32 clk_cfg_9_set
Definition: pll.h:51
mtk_topckgen_regs::clk_cfg_5_set
u32 clk_cfg_5_set
Definition: pll.h:38
mtk_topckgen_regs::aud_top_mon
u32 aud_top_mon
Definition: pll.h:78
mtk_topckgen_regs::reserved1
u32 reserved1[6]
Definition: pll.h:12
mtk_topckgen_regs::reserved17
u32 reserved17[53]
Definition: pll.h:80
mtk_topckgen_regs::reserved8
u32 reserved8[1]
Definition: pll.h:40
mtk_topckgen_regs::clk_cfg_7_clr
u32 clk_cfg_7_clr
Definition: pll.h:47
mtk_topckgen_regs::reserved12
u32 reserved12[9]
Definition: pll.h:56
mtk_topckgen_regs::clk_cfg_11
u32 clk_cfg_11
Definition: pll.h:60
mtk_topckgen_regs::reserved4
u32 reserved4[1]
Definition: pll.h:24
mtk_topckgen_regs::clk_cfg_2_clr
u32 clk_cfg_2_clr
Definition: pll.h:27
mtk_topckgen_regs::clk_cfg_4_set
u32 clk_cfg_4_set
Definition: pll.h:34
mtk_topckgen_regs::reserved15
u32 reserved15[2]
Definition: pll.h:70
mtk_topckgen_regs::clk_cfg_9_clr
u32 clk_cfg_9_clr
Definition: pll.h:52
mtk_topckgen_regs::clk_cfg_update1
u32 clk_cfg_update1
Definition: pll.h:12
mtk_topckgen_regs::clk_cfg_3_clr
u32 clk_cfg_3_clr
Definition: pll.h:31
mtk_topckgen_regs::clk_cfg_20
u32 clk_cfg_20
Definition: pll.h:85
mtk_topckgen_regs::clk_cfg_8
u32 clk_cfg_8
Definition: pll.h:57
mtk_topckgen_regs::clk_cfg_12
u32 clk_cfg_12
Definition: pll.h:49
mtk_topckgen_regs::clk_cfg_3_set
u32 clk_cfg_3_set
Definition: pll.h:30
mtk_topckgen_regs::reserved9
u32 reserved9[1]
Definition: pll.h:44
mtk_topckgen_regs::cksta_reg1
u32 cksta_reg1
Definition: pll.h:69
mtk_topckgen_regs::reserved3
u32 reserved3[1]
Definition: pll.h:20
mtk_topckgen_regs::clk_cfg_4
u32 clk_cfg_4
Definition: pll.h:33
mtk_topckgen_regs::clk_cfg_0
u32 clk_cfg_0
Definition: pll.h:17
mtk_topckgen_regs::reserved2
u32 reserved2[5]
Definition: pll.h:16
mtk_topckgen_regs::clk_cfg_6_clr
u32 clk_cfg_6_clr
Definition: pll.h:43
mtk_topckgen_regs::clk_cfg_8_clr
u32 clk_cfg_8_clr
Definition: pll.h:48
mtk_topckgen_regs::clk_cfg_7
u32 clk_cfg_7
Definition: pll.h:45
mtk_topckgen_regs::clk_cfg_10_set
u32 clk_cfg_10_set
Definition: pll.h:55
mtk_topckgen_regs::clk_cfg_1_set
u32 clk_cfg_1_set
Definition: pll.h:22
mtk_topckgen_regs::clk_cfg_8_set
u32 clk_cfg_8_set
Definition: pll.h:47
mtk_topckgen_regs::usb_top_cfg
u32 usb_top_cfg
Definition: pll.h:112
mtk_topckgen_regs::reserved5
u32 reserved5[1]
Definition: pll.h:28
mtk_topckgen_regs::reserved14
u32 reserved14[51]
Definition: pll.h:67
mtk_topckgen_regs::clk_dbg_cfg
u32 clk_dbg_cfg
Definition: pll.h:60
mtk_topckgen_regs::clk_cfg_10_clr
u32 clk_cfg_10_clr
Definition: pll.h:56
mtk_topckgen_regs::reserved18
u32 reserved18[50]
Definition: pll.h:80
mtk_topckgen_regs::clk_auddiv_2
u32 clk_auddiv_2
Definition: pll.h:64
mtk_topckgen_regs::clk_cfg_1_clr
u32 clk_cfg_1_clr
Definition: pll.h:23
mtk_topckgen_regs::clk_cfg_0_set
u32 clk_cfg_0_set
Definition: pll.h:18
mtk_topckgen_regs::clk_cfg_13
u32 clk_cfg_13
Definition: pll.h:53
mtk_topckgen_regs::clk_cfg_3
u32 clk_cfg_3
Definition: pll.h:29
mtk_topckgen_regs::clk_cfg_20_set
u32 clk_cfg_20_set
Definition: pll.h:86
mtk_topckgen_regs::clkmon_clk_sel_reg
u32 clkmon_clk_sel_reg
Definition: pll.h:71
mtk_topckgen_regs::clk_cfg_4_clr
u32 clk_cfg_4_clr
Definition: pll.h:35
mtk_topckgen_regs::clk26cali_0
u32 clk26cali_0
Definition: pll.h:75
mtk_topckgen_regs::clk_cfg_14_set
u32 clk_cfg_14_set
Definition: pll.h:76
mtk_topckgen_regs::clk_cfg_20_clr
u32 clk_cfg_20_clr
Definition: pll.h:87
mtk_topckgen_regs::clk_cfg_15
u32 clk_cfg_15
Definition: pll.h:88
mtk_topckgen_regs::clk_cfg_5
u32 clk_cfg_5
Definition: pll.h:37
mtk_topckgen_regs::clk_cfg_11_clr
u32 clk_cfg_11_clr
Definition: pll.h:65
mtk_topckgen_regs::reserved24
u32 reserved24[6]
Definition: pll.h:104
mtk_topckgen_regs::clk_cfg_0_clr
u32 clk_cfg_0_clr
Definition: pll.h:19
mtk_topckgen_regs::clk_cfg_14
u32 clk_cfg_14
Definition: pll.h:75
mtk_topckgen_regs::reserved6
u32 reserved6[1]
Definition: pll.h:32
mtk_topckgen_regs::clk_cfg_10
u32 clk_cfg_10
Definition: pll.h:59
mtk_topckgen_regs::clk_scp_cfg_0
u32 clk_scp_cfg_0
Definition: pll.h:68
mtk_topckgen_regs::clk_cfg_14_clr
u32 clk_cfg_14_clr
Definition: pll.h:77
mtk_topckgen_regs::reserved16
u32 reserved16[1]
Definition: pll.h:74
mtk_topckgen_regs::clk_cfg_2
u32 clk_cfg_2
Definition: pll.h:25
mtk_topckgen_regs::clk_cfg_5_clr
u32 clk_cfg_5_clr
Definition: pll.h:39
mtk_topckgen_regs::reserved20
u32 reserved20[79]
Definition: pll.h:84
mtk_topckgen_regs::clk_cfg_15_set
u32 clk_cfg_15_set
Definition: pll.h:89
mtk_topckgen_regs::reserved7
u32 reserved7[1]
Definition: pll.h:36
mtk_topckgen_regs::reserved10
u32 reserved10[1]
Definition: pll.h:48
mtk_topckgen_regs::clk26cali_1
u32 clk26cali_1
Definition: pll.h:76
mtk_topckgen_regs::clk_auddiv_3
u32 clk_auddiv_3
Definition: pll.h:65
mtk_topckgen_regs::clk_cfg_13_clr
u32 clk_cfg_13_clr
Definition: pll.h:55
mtk_topckgen_regs::clk_cfg_6_set
u32 clk_cfg_6_set
Definition: pll.h:42