pll_common.h File Reference

#include <device/mmio.h>
#include <soc/addressmap.h>
#include <types.h>

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Data Structures
struct	mux
struct	pll

Macros
#define	mtk_topckgen   ((struct mtk_topckgen_regs *)CKSYS_BASE)
#define	mtk_apmixed   ((struct mtk_apmixed_regs *)APMIXED_BASE)
#define	PLL_PWR_ON   (1 << 0)
#define	PLL_EN   (1 << 0)
#define	PLL_ISO   (1 << 1)
#define	PLL_RSTB_SHIFT   (24)
#define	NO_RSTB_SHIFT   (255)
#define	PLL_PCW_CHG   (1 << 31)
#define	PLL_POSTDIV_MASK   0x7
#define	PLL(_id, _reg, _pwr_reg, _rstb, _pcwbits, _div_reg, _div_shift, _pcw_reg, _pcw_shift, _div_rate)

Enumerations
enum	fmeter_type { FMETER_ABIST = 0 , FMETER_CKGEN }

Functions
void	pll_set_pcw_change (const struct pll *pll)
void	mux_set_sel (const struct mux *mux, u32 sel)
int	pll_set_rate (const struct pll *pll, u32 rate)
void	mt_pll_init (void)
void	mt_pll_raise_little_cpu_freq (u32 freq)
void	mt_pll_raise_cci_freq (u32 freq)
void	mt_pll_set_tvd_pll1_freq (u32 freq)
void	edp_mux_set_sel (u32 sel)
u32	mt_fmeter_get_freq_khz (enum fmeter_type type, u32 id)

Macro Definition Documentation

mtk_apmixed

#define mtk_apmixed   ((struct mtk_apmixed_regs *)APMIXED_BASE)

Definition at line 12 of file pll_common.h.

mtk_topckgen

#define mtk_topckgen   ((struct mtk_topckgen_regs *)CKSYS_BASE)

Definition at line 11 of file pll_common.h.

NO_RSTB_SHIFT

#define NO_RSTB_SHIFT   (255)

Definition at line 18 of file pll_common.h.

PLL

#define PLL	(		_id,
			_reg,
			_pwr_reg,
			_rstb,
			_pcwbits,
			_div_reg,
			_div_shift,
			_pcw_reg,
			_pcw_shift,
			_div_rate
	)

Value:

        [_id] = {                                                       \
                .reg = &mtk_apmixed->_reg,                              \
                .pwr_reg = &mtk_apmixed->_pwr_reg,                      \
                .rstb_shift = _rstb,                                    \
                .pcwbits = _pcwbits,                                    \
                .div_reg = &mtk_apmixed->_div_reg,                      \
                .div_shift = _div_shift,                                \
                .pcw_reg = &mtk_apmixed->_pcw_reg,                      \
                .pcw_shift = _pcw_shift,                                \
                .div_rate = _div_rate,                                  \
        }

Definition at line 44 of file pll_common.h.

PLL_EN

#define PLL_EN   (1 << 0)

Definition at line 15 of file pll_common.h.

PLL_ISO

#define PLL_ISO   (1 << 1)

Definition at line 16 of file pll_common.h.

PLL_PCW_CHG

#define PLL_PCW_CHG   (1 << 31)

Definition at line 19 of file pll_common.h.

PLL_POSTDIV_MASK

#define PLL_POSTDIV_MASK   0x7

Definition at line 20 of file pll_common.h.

PLL_PWR_ON

#define PLL_PWR_ON   (1 << 0)

Definition at line 14 of file pll_common.h.

PLL_RSTB_SHIFT

#define PLL_RSTB_SHIFT   (24)

Definition at line 17 of file pll_common.h.

Enumeration Type Documentation

fmeter_type

enum fmeter_type

Enumerator
FMETER_ABIST
FMETER_CKGEN

Definition at line 76 of file pll_common.h.

Function Documentation

edp_mux_set_sel()

void edp_mux_set_sel

(

u32

sel

)

Definition at line 830 of file pll.c.

References mux_set_sel(), muxes, and TOP_EDP_SEL.

Referenced by mtk_dpintf_power_on().

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mt_fmeter_get_freq_khz()

u32 mt_fmeter_get_freq_khz	(	enum fmeter_type	type,
		u32	id
	)

Definition at line 519 of file pll.c.

References BIOS_WARNING, count, die(), FMETER_ABIST, FMETER_CKGEN, mtk_topckgen, printk, read32(), READ32_BITFIELD, SET32_BITFIELDS, type, wait_us, and write32().

Referenced by pmif_get_ulposc_freq_mhz(), and raise_little_cpu_freq().

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mt_pll_init()

void mt_pll_init

(

void

)

Definition at line 289 of file pll.c.

References mtk_spm_regs::ap_mdsrc_req, APMIXED_APLL5, APMIXED_NR_PLL, APMIXED_PLL_MAX, APMIXED_USBPLL, ARMPLL_DIVIDER_PLL1_EN, ARMPLL_DIVIDER_PLL2_EN, ARRAY_SIZE, mt8195_scp_adsp_regs::audiodsp_ck_cg, BIT, mt8183_mcucfg_regs::bus_pll_divider_cfg, mt8186_mcucfg_regs::bus_plldiv_cfg, clrbits32, clrsetbits32, mt8186_mcucfg_regs::cpu_plldiv_cfg0, mt8186_mcucfg_regs::cpu_plldiv_cfg1, DCM_INFRA_BUS_MASK, DCM_INFRA_BUS_ON, DCM_INFRA_MEM_ON, DCM_INFRA_P2PRX_MASK, DCM_INFRA_PERI_MASK, DCM_INFRA_PERI_ON, DIV_1, DIV_2, DIV_MASK, GLITCH_FREE_EN, mt8192_infracfg_regs::infra_aximem_idle_bit_en_0, mt8195_infracfg_ao_regs::infra_aximem_idle_bit_en_0, mt8183_infracfg_regs::infra_bus_dcm_ctrl, mt8186_infracfg_ao_regs::infra_bus_dcm_ctrl, mt8192_infracfg_regs::infra_bus_dcm_ctrl, mt8195_infracfg_ao_regs::infra_bus_dcm_ctrl, INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK, INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON, INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK, INFRACFG_AO_INFRA_BUS_DCM_REG0_ON, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON, INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK, INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON, INFRACFG_AO_PERI_BUS_DCM_REG0_MASK, INFRACFG_AO_PERI_BUS_DCM_REG0_ON, INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK, INFRACFG_AO_PERI_MODULE_DCM_REG0_ON, MCU_DIV_1, MCU_DIV_MASK, MCU_MUX_MASK, MCU_MUX_SRC_PLL, mt8183_infracfg_regs::mem_dcm_ctrl, MHz, mt8183_infracfg_regs::module_clk_sel, mt8186_infracfg_ao_regs::module_sw_cg_0_clr, mt8195_infracfg_ao_regs::module_sw_cg_0_clr, mt8183_infracfg_regs::module_sw_cg_1_clr, mt8186_infracfg_ao_regs::module_sw_cg_1_clr, mt8195_infracfg_ao_regs::module_sw_cg_1_clr, mt8183_infracfg_regs::module_sw_cg_2_clr, mt8192_infracfg_regs::module_sw_cg_2_clr, mt8195_infracfg_ao_regs::module_sw_cg_2_clr, mt8192_infracfg_regs::module_sw_cg_2_set, mt8186_infracfg_ao_regs::module_sw_cg_3_clr, mt8195_infracfg_ao_regs::module_sw_cg_3_clr, mt8183_mcucfg_regs::mp0_pll_divider_cfg, mt8183_mcucfg_regs::mp2_pll_divider_cfg, mt8173_infracfg, mt8183_infracfg, mt8183_mcucfg, mt8186_infracfg_ao, MT8186_PLL_EN, mt8192_infracfg, MT8195_APLL5_EN, mt8195_infracfg_ao, mt8195_infracfg_ao_bcrm, mt8195_pericfg_ao, MT8195_PLL_EN, mt8195_scp_adsp, mtk_apmixed, mtk_mcucfg, mtk_spm, mtk_topckgen, mtk_wdt, MUX_MASK, mux_sels, mux_set_sel(), MUX_SRC_ARMPLL, muxes, NO_RSTB_SHIFT, mt8183_infracfg_regs::p2p_rx_clk_on, mt8186_infracfg_ao_regs::p2p_rx_clk_on, mt8192_infracfg_regs::p2p_rx_clk_on, mt8195_infracfg_ao_regs::p2p_rx_clk_on, mt8183_infracfg_regs::peri_bus_dcm_ctrl, mt8186_infracfg_ao_regs::peri_bus_dcm_ctrl, mt8192_infracfg_regs::peri_bus_dcm_ctrl, mt8195_infracfg_ao_regs::peri_bus_dcm_ctrl, mt8195_pericfg_ao_regs::peri_module_sw_cg_0_set, PLL_CKSQ_ON_DELAY, PLL_DIV_EN, PLL_EN, PLL_EN_DELAY, PLL_ISO, PLL_ISO_DELAY, PLL_PWR_ON, PLL_PWR_ON_DELAY, pll_set_rate(), plls, rates, read32(), SET32_BITFIELDS, setbits32, mt8173_infracfg_regs::top_dcmctl, udelay(), USBPLL_EN, mt8195_infracfg_ao_bcrm_regs::vdnr_dcm_top_infra_ctrl0, mtk_wdt_regs::wdt_swsysrst, and write32().

Referenced by bootblock_soc_init().

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mt_pll_raise_cci_freq()

void mt_pll_raise_cci_freq

(

u32

freq

)

Definition at line 500 of file pll.c.

References APMIXED_CCIPLL, mt8186_mcucfg_regs::bus_plldiv_cfg, clrbits32, clrsetbits32, MCU_MUX_MASK, MCU_MUX_SRC_26M, MCU_MUX_SRC_DIV_PLL1, MCU_MUX_SRC_PLL, MT8186_PLL_EN, MT8195_PLL_EN, mtk_mcucfg, mtk_topckgen, PLL_EN, PLL_EN_DELAY, pll_set_rate(), plls, setbits32, and udelay().

Referenced by raise_little_cpu_freq().

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mt_pll_raise_little_cpu_freq()

void mt_pll_raise_little_cpu_freq

(

u32

freq

)

Definition at line 420 of file pll.c.

References APMIXED_ARMCA7PLL, APMIXED_ARMPLL_LL, clrbits32, clrsetbits32, mt8186_mcucfg_regs::cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M, MCU_MUX_SRC_DIV_PLL1, MCU_MUX_SRC_PLL, mt8183_mcucfg_regs::mp0_pll_divider_cfg, mt8183_mcucfg, MT8186_PLL_EN, MT8195_PLL_EN, mtk_mcucfg, mtk_topckgen, MUX_MASK, MUX_SRC_ARMPLL, MUX_SRC_DIV_PLL1, PLL_EN, PLL_EN_DELAY, pll_set_rate(), plls, setbits32, and udelay().

Referenced by platform_romstage_main(), and raise_little_cpu_freq().

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mt_pll_set_tvd_pll1_freq()

void mt_pll_set_tvd_pll1_freq

(

u32

freq

)

Definition at line 817 of file pll.c.

References APMIXED_TVDPLL1, clrbits32, MT8195_PLL_EN, PLL_EN_DELAY, pll_set_rate(), plls, setbits32, and udelay().

Referenced by mtk_dpintf_power_on().

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mux_set_sel()

void mux_set_sel	(	const struct mux *	mux,
		u32	sel
	)

Definition at line 8 of file pll.c.

References mux::clr_reg, GENMASK, mask, mux::mux_shift, mux::mux_width, read32(), mux::reg, mux::set_reg, mux::upd_reg, mux::upd_shift, val, and write32().

Referenced by edp_mux_set_sel(), and mt_pll_init().

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pll_set_pcw_change()

void pll_set_pcw_change

(

const struct pll *

pll

)

Definition at line 284 of file pll.c.

References pll::div_reg, pll::pcw_reg, PLL_PCW_CHG, and setbits32.

Referenced by pll_set_rate_regs().

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pll_set_rate()

int pll_set_rate	(	const struct pll *	pll,
		u32	rate
	)

Definition at line 72 of file pll.c.

References pll_calc_values(), and pll_set_rate_regs().

Referenced by mt_pll_init(), mt_pll_raise_cci_freq(), mt_pll_raise_little_cpu_freq(), and mt_pll_set_tvd_pll1_freq().

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