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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <bootblock_common.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/pei_data.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6779d/nct6779d.h>
#include <option.h>
Go to the source code of this file.
Macros | |
#define | SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) |
Functions | |
void | bootblock_mainboard_early_init (void) |
void | mainboard_get_spd (spd_raw_data *spd, bool id_only) |
int | mainboard_should_reset_usb (int s3resume) |
void | mainboard_fill_pei_data (struct pei_data *pei) |
Variables | |
const struct southbridge_usb_port | mainboard_usb_ports [] |
#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) |
Definition at line 14 of file early_init.c.
Definition at line 34 of file early_init.c.
References nuvoton_enable_serial(), and SERIAL_DEV.
Definition at line 58 of file early_init.c.
References pei_data::ddr3lv_support, pei_data::gbe_enable, get_uint_option(), pch_usb3_controller_settings::hs_port_switch_mask, pei_data::max_ddr3_freq, memcpy(), pch_usb3_controller_settings::mode, pei_data::pcie_init, pch_usb3_controller_settings::preboot_support, pei_data::spd_addresses, pei_data::usb3, pei_data::usb_port_config, and pch_usb3_controller_settings::xhci_streams.
Referenced by broadwell_run_reference_code(), and perform_raminit().
void mainboard_get_spd | ( | spd_raw_data * | spd, |
bool | id_only | ||
) |
Definition at line 45 of file early_init.c.
References read_spd().
int mainboard_should_reset_usb | ( | int | s3resume | ) |
Definition at line 53 of file early_init.c.
Referenced by perform_raminit().
const struct southbridge_usb_port mainboard_usb_ports[] |
Definition at line 1 of file early_init.c.