coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
report_platform.c File Reference
#include <arch/cpu.h>
#include <device/pci_ops.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <cpu/intel/cpu_ids.h>
#include <cpu/intel/microcode.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/name.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <soc/bootblock.h>
#include <soc/pci_devs.h>
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Functions

static uint8_t get_dev_revision (pci_devfn_t dev)
 
static uint16_t get_dev_id (pci_devfn_t dev)
 
static void report_cache_info (void)
 
static void report_cpu_info (void)
 
static void report_mch_info (void)
 
static void report_pch_info (void)
 
static void report_igd_info (void)
 
void report_platform_info (void)
 

Variables

struct {
   u32   cpuid
 
   const char *   name
 
cpu_table []
 
struct {
   u16   mchid
 
   const char *   name
 
mch_table []
 
struct {
   u16   espiid
 
   const char *   name
 
pch_table []
 
struct {
   u16   igdid
 
   const char *   name
 
igd_table []
 

Function Documentation

◆ get_dev_id()

static uint16_t get_dev_id ( pci_devfn_t  dev)
inlinestatic

Definition at line 137 of file report_platform.c.

References PCI_DEVICE_ID, and pci_read_config16().

Referenced by report_igd_info(), report_mch_info(), and report_pch_info().

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◆ get_dev_revision()

static uint8_t get_dev_revision ( pci_devfn_t  dev)
inlinestatic

Definition at line 132 of file report_platform.c.

References pci_read_config8(), and PCI_REVISION_ID.

Referenced by report_igd_info(), report_mch_info(), and report_pch_info().

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◆ report_cache_info()

static void report_cache_info ( void  )
static

Definition at line 142 of file report_platform.c.

References BIOS_INFO, CACHE_L3, fill_cpu_cache_info(), get_cache_size(), info, MiB, and printk.

Referenced by report_cpu_info().

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◆ report_cpu_info()

static void report_cpu_info ( void  )
static

Definition at line 157 of file report_platform.c.

References ARRAY_SIZE, BIOS_DEBUG, cpu_get_cpuid(), cpu_get_feature_flags_ecx(), cpu_id, cpu_table, cpuid, CPUID_AES, CPUID_SMX, CPUID_VMX, fill_processor_name(), get_current_microcode_rev(), printk, and report_cache_info().

Referenced by report_platform_info().

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◆ report_igd_info()

static void report_igd_info ( void  )
static

Definition at line 225 of file report_platform.c.

References ARRAY_SIZE, BIOS_DEBUG, get_dev_id(), get_dev_revision(), igd_table, igdid, printk, and SA_DEV_IGD.

Referenced by report_platform_info().

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◆ report_mch_info()

static void report_mch_info ( void  )
static

Definition at line 191 of file report_platform.c.

References ARRAY_SIZE, BIOS_DEBUG, get_dev_id(), get_dev_revision(), mch_table, mchid, printk, and SA_DEV_ROOT.

Referenced by report_platform_info().

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◆ report_pch_info()

static void report_pch_info ( void  )
static

Definition at line 208 of file report_platform.c.

References ARRAY_SIZE, BIOS_DEBUG, espiid, get_dev_id(), get_dev_revision(), PCH_DEV_ESPI, pch_table, pch_type(), and printk.

Referenced by report_platform_info().

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◆ report_platform_info()

void report_platform_info ( void  )

Definition at line 242 of file report_platform.c.

References report_cpu_info(), report_igd_info(), report_mch_info(), and report_pch_info().

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Variable Documentation

◆ 

struct { ... } cpu_table[]
Initial value:
= {
{ CPUID_ALDERLAKE_J0, "Alderlake J0 Platform" },
{ CPUID_ALDERLAKE_K0, "Alderlake K0 Platform" },
{ CPUID_ALDERLAKE_L0, "Alderlake L0 Platform" },
{ CPUID_ALDERLAKE_Q0, "Alderlake Q0 Platform" },
{ CPUID_ALDERLAKE_R0, "Alderlake R0 Platform" },
{ CPUID_ALDERLAKE_N_A0, "Alderlake-N Platform" },
}
#define CPUID_ALDERLAKE_K0
Definition: cpu_ids.h:56
#define CPUID_ALDERLAKE_J0
Definition: cpu_ids.h:54
#define CPUID_ALDERLAKE_R0
Definition: cpu_ids.h:58
#define CPUID_ALDERLAKE_N_A0
Definition: cpu_ids.h:59
#define CPUID_ALDERLAKE_L0
Definition: cpu_ids.h:57
#define CPUID_ALDERLAKE_Q0
Definition: cpu_ids.h:55

Referenced by report_cpu_info().

◆ cpuid

◆ espiid

u16 espiid

Definition at line 57 of file report_platform.c.

Referenced by report_pch_info().

◆ 

struct { ... } igd_table[]
Initial value:
= {
{ PCI_DID_INTEL_ADL_GT0, "Alderlake GT0" },
{ PCI_DID_INTEL_ADL_GT1, "Alderlake GT1" },
{ PCI_DID_INTEL_ADL_GT1_1, "Alderlake GT1" },
{ PCI_DID_INTEL_ADL_GT1_2, "Alderlake GT1" },
{ PCI_DID_INTEL_ADL_GT1_3, "Alderlake GT1" },
{ PCI_DID_INTEL_ADL_GT1_4, "Alderlake GT1" },
{ PCI_DID_INTEL_ADL_GT1_5, "Alderlake GT1" },
{ PCI_DID_INTEL_ADL_GT1_6, "Alderlake GT1" },
{ PCI_DID_INTEL_ADL_GT1_7, "Alderlake GT1" },
{ PCI_DID_INTEL_ADL_GT1_8, "Alderlake GT1" },
{ PCI_DID_INTEL_ADL_GT1_9, "Alderlake GT1" },
{ PCI_DID_INTEL_ADL_P_GT2, "Alderlake P GT2" },
{ PCI_DID_INTEL_ADL_P_GT2_1, "Alderlake P GT2" },
{ PCI_DID_INTEL_ADL_P_GT2_2, "Alderlake P GT2" },
{ PCI_DID_INTEL_ADL_P_GT2_3, "Alderlake P GT2" },
{ PCI_DID_INTEL_ADL_P_GT2_4, "Alderlake P GT2" },
{ PCI_DID_INTEL_ADL_P_GT2_5, "Alderlake P GT2" },
{ PCI_DID_INTEL_ADL_P_GT2_6, "Alderlake P GT2" },
{ PCI_DID_INTEL_ADL_P_GT2_7, "Alderlake P GT2" },
{ PCI_DID_INTEL_ADL_P_GT2_8, "Alderlake P GT2" },
{ PCI_DID_INTEL_ADL_P_GT2_9, "Alderlake P GT2" },
{ PCI_DID_INTEL_ADL_M_GT1, "Alderlake M GT1" },
{ PCI_DID_INTEL_ADL_M_GT2, "Alderlake M GT2" },
{ PCI_DID_INTEL_ADL_M_GT3, "Alderlake M GT3" },
{ PCI_DID_INTEL_ADL_N_GT1, "Alderlake N GT1" },
{ PCI_DID_INTEL_ADL_N_GT2, "Alderlake N GT2" },
{ PCI_DID_INTEL_ADL_N_GT3, "Alderlake N GT3" },
}
#define PCI_DID_INTEL_ADL_P_GT2_5
Definition: pci_ids.h:3947
#define PCI_DID_INTEL_ADL_N_GT1
Definition: pci_ids.h:3956
#define PCI_DID_INTEL_ADL_GT1_6
Definition: pci_ids.h:3938
#define PCI_DID_INTEL_ADL_GT1_8
Definition: pci_ids.h:3940
#define PCI_DID_INTEL_ADL_GT1_3
Definition: pci_ids.h:3935
#define PCI_DID_INTEL_ADL_P_GT2_2
Definition: pci_ids.h:3944
#define PCI_DID_INTEL_ADL_GT1_5
Definition: pci_ids.h:3937
#define PCI_DID_INTEL_ADL_M_GT1
Definition: pci_ids.h:3953
#define PCI_DID_INTEL_ADL_P_GT2
Definition: pci_ids.h:3942
#define PCI_DID_INTEL_ADL_P_GT2_7
Definition: pci_ids.h:3949
#define PCI_DID_INTEL_ADL_P_GT2_3
Definition: pci_ids.h:3945
#define PCI_DID_INTEL_ADL_P_GT2_8
Definition: pci_ids.h:3950
#define PCI_DID_INTEL_ADL_P_GT2_1
Definition: pci_ids.h:3943
#define PCI_DID_INTEL_ADL_GT1_4
Definition: pci_ids.h:3936
#define PCI_DID_INTEL_ADL_GT1_9
Definition: pci_ids.h:3941
#define PCI_DID_INTEL_ADL_M_GT2
Definition: pci_ids.h:3954
#define PCI_DID_INTEL_ADL_P_GT2_4
Definition: pci_ids.h:3946
#define PCI_DID_INTEL_ADL_N_GT2
Definition: pci_ids.h:3957
#define PCI_DID_INTEL_ADL_P_GT2_6
Definition: pci_ids.h:3948
#define PCI_DID_INTEL_ADL_P_GT2_9
Definition: pci_ids.h:3951
#define PCI_DID_INTEL_ADL_GT1_7
Definition: pci_ids.h:3939
#define PCI_DID_INTEL_ADL_GT1_1
Definition: pci_ids.h:3933
#define PCI_DID_INTEL_ADL_GT1
Definition: pci_ids.h:3932
#define PCI_DID_INTEL_ADL_GT0
Definition: pci_ids.h:3931
#define PCI_DID_INTEL_ADL_M_GT3
Definition: pci_ids.h:3955
#define PCI_DID_INTEL_ADL_N_GT3
Definition: pci_ids.h:3958
#define PCI_DID_INTEL_ADL_GT1_2
Definition: pci_ids.h:3934

Referenced by report_igd_info().

◆ igdid

u16 igdid

Definition at line 100 of file report_platform.c.

Referenced by report_igd_info().

◆ 

struct { ... } mch_table[]
Initial value:
= {
{ PCI_DID_INTEL_ADL_P_ID_1, "Alderlake-P" },
{ PCI_DID_INTEL_ADL_P_ID_3, "Alderlake-P" },
{ PCI_DID_INTEL_ADL_P_ID_4, "Alderlake-P" },
{ PCI_DID_INTEL_ADL_P_ID_5, "Alderlake-P" },
{ PCI_DID_INTEL_ADL_P_ID_6, "Alderlake-P" },
{ PCI_DID_INTEL_ADL_P_ID_7, "Alderlake-P" },
{ PCI_DID_INTEL_ADL_P_ID_8, "Alderlake-P" },
{ PCI_DID_INTEL_ADL_P_ID_9, "Alderlake-P" },
{ PCI_DID_INTEL_ADL_P_ID_10, "Alderlake-P" },
{ PCI_DID_INTEL_ADL_M_ID_1, "Alderlake-M" },
{ PCI_DID_INTEL_ADL_M_ID_2, "Alderlake-M" },
{ PCI_DID_INTEL_ADL_N_ID_1, "Alderlake-N" },
{ PCI_DID_INTEL_ADL_N_ID_2, "Alderlake-N" },
{ PCI_DID_INTEL_ADL_N_ID_3, "Alderlake-N" },
{ PCI_DID_INTEL_ADL_N_ID_4, "Alderlake-N" },
}
#define PCI_DID_INTEL_ADL_P_ID_7
Definition: pci_ids.h:4069
#define PCI_DID_INTEL_ADL_N_ID_2
Definition: pci_ids.h:4076
#define PCI_DID_INTEL_ADL_P_ID_4
Definition: pci_ids.h:4066
#define PCI_DID_INTEL_ADL_P_ID_3
Definition: pci_ids.h:4065
#define PCI_DID_INTEL_ADL_P_ID_5
Definition: pci_ids.h:4067
#define PCI_DID_INTEL_ADL_N_ID_4
Definition: pci_ids.h:4078
#define PCI_DID_INTEL_ADL_P_ID_10
Definition: pci_ids.h:4072
#define PCI_DID_INTEL_ADL_P_ID_6
Definition: pci_ids.h:4068
#define PCI_DID_INTEL_ADL_P_ID_9
Definition: pci_ids.h:4071
#define PCI_DID_INTEL_ADL_N_ID_1
Definition: pci_ids.h:4075
#define PCI_DID_INTEL_ADL_M_ID_1
Definition: pci_ids.h:4073
#define PCI_DID_INTEL_ADL_P_ID_1
Definition: pci_ids.h:4064
#define PCI_DID_INTEL_ADL_P_ID_8
Definition: pci_ids.h:4070
#define PCI_DID_INTEL_ADL_N_ID_3
Definition: pci_ids.h:4077
#define PCI_DID_INTEL_ADL_M_ID_2
Definition: pci_ids.h:4074

Referenced by report_mch_info().

◆ mchid

◆ name

const char* name

Definition at line 24 of file report_platform.c.

◆ 

struct { ... } pch_table[]

Referenced by report_pch_info().