coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
ramstage.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <
acpi/acpi_device.h
>
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#include <baseboard/variants.h>
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#include <
console/console.h
>
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#include <
device/pci_ops.h
>
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#include <soc/pci_devs.h>
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#include <
drivers/intel/dptf/chip.h
>
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#include <
intelblocks/power_limit.h
>
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WEAK_DEV_PTR
(dptf_policy);
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void
variant_update_power_limits
(
const
struct
cpu_power_limits
*
limits
,
size_t
num_entries)
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{
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if
(!num_entries)
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return
;
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const
struct
device
*policy_dev =
DEV_PTR
(dptf_policy);
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if
(!policy_dev)
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return
;
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struct
drivers_intel_dptf_config
*
config
= policy_dev->
chip_info
;
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uint16_t
mchid
=
pci_s_read_config16
(
PCI_DEV
(0, 0, 0),
PCI_DEVICE_ID
);
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u8
tdp =
get_cpu_tdp
();
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for
(
size_t
i = 0; i < num_entries; i++) {
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if
(
mchid
==
limits
[i].
mchid
&& tdp ==
limits
[i].
cpu_tdp
) {
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struct
dptf_power_limits
*settings = &
config
->controls.power_limits;
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config_t
*conf =
config_of_soc
();
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struct
soc_power_limits_config
*soc_config = conf->power_limits_config;
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settings->
pl1
.
min_power
=
limits
[i].
pl1_min_power
;
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settings->
pl1
.
max_power
=
limits
[i].
pl1_max_power
;
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settings->
pl2
.
min_power
=
limits
[i].
pl2_min_power
;
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settings->
pl2
.
max_power
=
limits
[i].
pl2_max_power
;
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soc_config->
tdp_pl4
=
DIV_ROUND_UP
(
limits
[i].pl4_power,
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MILLIWATTS_TO_WATTS
);
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printk
(
BIOS_INFO
,
"Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n"
,
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limits
[i].pl1_min_power,
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limits
[i].pl1_max_power,
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limits
[i].pl2_min_power,
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limits
[i].pl2_max_power,
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limits
[i].pl4_power);
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}
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}
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}
acpi_device.h
DIV_ROUND_UP
#define DIV_ROUND_UP(x, y)
Definition:
helpers.h:60
printk
#define printk(level,...)
Definition:
stdlib.h:16
console.h
chip.h
DEV_PTR
#define DEV_PTR(_alias)
Definition:
device.h:403
config_of_soc
#define config_of_soc()
Definition:
device.h:394
pci_ops.h
BIOS_INFO
#define BIOS_INFO
BIOS_INFO - Expected events.
Definition:
loglevel.h:113
variant_update_power_limits
void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries)
Definition:
ramstage.c:51
WEAK_DEV_PTR
WEAK_DEV_PTR(dptf_policy)
limits
const struct cpu_power_limits limits[]
Definition:
ramstage.c:11
config
enum board_config config
Definition:
memory.c:448
PCI_DEVICE_ID
#define PCI_DEVICE_ID
Definition:
pci_def.h:9
pci_s_read_config16
static __always_inline uint16_t pci_s_read_config16(pci_devfn_t dev, uint16_t reg)
Definition:
pci_io_cfg.h:86
PCI_DEV
#define PCI_DEV(SEGBUS, DEV, FN)
Definition:
pci_type.h:14
power_limit.h
MILLIWATTS_TO_WATTS
#define MILLIWATTS_TO_WATTS
Definition:
power_limit.h:18
get_cpu_tdp
u8 get_cpu_tdp(void)
Definition:
power_limit.c:199
mchid
u16 mchid
Definition:
report_platform.c:35
cpu_tdp
enum soc_intel_alderlake_cpu_tdps cpu_tdp
Definition:
chip.h:49
uint16_t
unsigned short uint16_t
Definition:
stdint.h:11
u8
uint8_t u8
Definition:
stdint.h:45
cpu_power_limits
Definition:
variants.h:39
cpu_power_limits::pl1_min_power
unsigned int pl1_min_power
Definition:
variants.h:42
cpu_power_limits::pl1_max_power
unsigned int pl1_max_power
Definition:
variants.h:43
cpu_power_limits::pl2_max_power
unsigned int pl2_max_power
Definition:
variants.h:45
cpu_power_limits::pl2_min_power
unsigned int pl2_min_power
Definition:
variants.h:44
device
Definition:
device.h:107
device::chip_info
DEVTREE_CONST void * chip_info
Definition:
device.h:164
dptf_power_limit_config::max_power
uint32_t max_power
Definition:
acpigen_dptf.h:123
dptf_power_limit_config::min_power
uint32_t min_power
Definition:
acpigen_dptf.h:121
dptf_power_limits
Definition:
acpigen_dptf.h:133
dptf_power_limits::pl2
struct dptf_power_limit_config pl2
Definition:
acpigen_dptf.h:135
dptf_power_limits::pl1
struct dptf_power_limit_config pl1
Definition:
acpigen_dptf.h:134
drivers_intel_dptf_config
Definition:
chip.h:18
ec_kontron_it8516e_config
Definition:
chip.h:8
soc_power_limits_config
Definition:
power_limit.h:20
soc_power_limits_config::tdp_pl4
uint16_t tdp_pl4
Definition:
power_limit.h:34
src
mainboard
google
brya
variants
baseboard
brya
ramstage.c
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