coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
ramstage.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <acpi/acpi_device.h>
4 #include <baseboard/variants.h>
5 #include <console/console.h>
6 #include <device/pci_ops.h>
7 #include <soc/pci_devs.h>
8 
11 
12 WEAK_DEV_PTR(dptf_policy);
13 
14 void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries)
15 {
16  if (!num_entries)
17  return;
18 
19  const struct device *policy_dev = DEV_PTR(dptf_policy);
20  if (!policy_dev)
21  return;
22 
23  struct drivers_intel_dptf_config *config = policy_dev->chip_info;
24 
26 
27  u8 tdp = get_cpu_tdp();
28 
29  for (size_t i = 0; i < num_entries; i++) {
30  if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) {
31  struct dptf_power_limits *settings = &config->controls.power_limits;
32  config_t *conf = config_of_soc();
33  struct soc_power_limits_config *soc_config = conf->power_limits_config;
34  settings->pl1.min_power = limits[i].pl1_min_power;
35  settings->pl1.max_power = limits[i].pl1_max_power;
36  settings->pl2.min_power = limits[i].pl2_min_power;
37  settings->pl2.max_power = limits[i].pl2_max_power;
38  soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power,
40  printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n",
41  limits[i].pl1_min_power,
42  limits[i].pl1_max_power,
43  limits[i].pl2_min_power,
44  limits[i].pl2_max_power,
45  limits[i].pl4_power);
46  }
47  }
48 }
#define DIV_ROUND_UP(x, y)
Definition: helpers.h:60
#define printk(level,...)
Definition: stdlib.h:16
#define DEV_PTR(_alias)
Definition: device.h:403
#define config_of_soc()
Definition: device.h:394
#define BIOS_INFO
BIOS_INFO - Expected events.
Definition: loglevel.h:113
void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries)
Definition: ramstage.c:51
WEAK_DEV_PTR(dptf_policy)
const struct cpu_power_limits limits[]
Definition: ramstage.c:11
enum board_config config
Definition: memory.c:448
#define PCI_DEVICE_ID
Definition: pci_def.h:9
static __always_inline uint16_t pci_s_read_config16(pci_devfn_t dev, uint16_t reg)
Definition: pci_io_cfg.h:86
#define PCI_DEV(SEGBUS, DEV, FN)
Definition: pci_type.h:14
#define MILLIWATTS_TO_WATTS
Definition: power_limit.h:18
u8 get_cpu_tdp(void)
Definition: power_limit.c:199
u16 mchid
enum soc_intel_alderlake_cpu_tdps cpu_tdp
Definition: chip.h:49
unsigned short uint16_t
Definition: stdint.h:11
uint8_t u8
Definition: stdint.h:45
unsigned int pl1_min_power
Definition: variants.h:42
unsigned int pl1_max_power
Definition: variants.h:43
unsigned int pl2_max_power
Definition: variants.h:45
unsigned int pl2_min_power
Definition: variants.h:44
Definition: device.h:107
DEVTREE_CONST void * chip_info
Definition: device.h:164
struct dptf_power_limit_config pl2
Definition: acpigen_dptf.h:135
struct dptf_power_limit_config pl1
Definition: acpigen_dptf.h:134