12 static void update_hsio_info_for_m2_slots(
size_t num_of_entry, BL_HSIO_INFORMATION *
config)
15 bool m2a_pcie, m2b_pcie;
23 supported_hsio_lanes =
24 (
uint16_t)fiamux_hob_data->FiaMuxConfig.SkuNumLanesAllowed;
35 "GPIO values from M2 slots A:%d B:%d "
36 "(0=SATA, 1=PCIe or not populated)\n",
41 for (entry = 0; entry < num_of_entry; entry++) {
43 if (
config[entry].NumLanesSupported != supported_hsio_lanes)
45 BL_ME_FIA_CONFIG *fia_config = &(
config[entry].FiaConfig);
46 BL_ME_FIA_MUX_CONFIG *mux_config =
47 &(
config[entry].FiaConfig.MuxConfiguration);
48 BL_ME_FIA_SATA_CONFIG *sata_config =
49 &(
config[entry].FiaConfig.SataLaneConfiguration);
52 mux_config->BL_MeFiaMuxLaneMuxSel.Lane14MuxSel =
53 BL_ME_FIA_MUX_LANE_SATA;
54 sata_config->BL_MeFiaSataLaneSataSel.Lane14SataSel =
55 BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED;
59 mux_config->BL_MeFiaMuxLaneMuxSel.Lane12MuxSel =
60 BL_ME_FIA_MUX_LANE_SATA;
61 sata_config->BL_MeFiaSataLaneSataSel.Lane12SataSel =
62 BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED;
70 && (!m2a_pcie || !m2b_pcie)
72 &fiamux_hob_data->FiaMuxConfig.FiaMuxConfig,
73 sizeof(BL_ME_FIA_CONFIG))) {
77 &fiamux_hob_data->FiaMuxConfig.FiaMuxConfig,
78 sizeof(BL_ME_FIA_CONFIG));
80 "M2 SATA Slots are not available!\n");
static uint32_t read32(const void *addr)
void * memcpy(void *dest, const void *src, size_t n)
#define printk(level,...)
#define PCH_PCR_ADDRESS(Pid, Offset)
void * fast_spi_get_bar(void)
#define SPIBAR_HSFSTS_FDOPSS
#define SPIBAR_HSFSTS_CTL
BL_FIA_MUX_CONFIG_HOB * get_fiamux_hob_data(void)
size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config)
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
#define BIOS_CRIT
BIOS_CRIT - Recovery unlikely.
#define R_PAD_CFG_DW0_GPIO_5
#define R_PAD_CFG_DW0_GPIO_4
DEVTREE_CONST BL_HSIO_INFORMATION tagada_hsio_config[]
#define B_PCH_GPIO_RX_STATE
int memcmp(const void *s1, const void *s2, size_t n)