coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
hsio.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <arch/mmio.h>
4 #include <console/console.h>
5 #include <hsio.h>
6 #include <gpio_defs.h>
7 #include <soc/fiamux.h>
8 #include <string.h>
9 #include <fast_spi_def.h>
10 
11 #ifdef __RAMSTAGE__
12 static void update_hsio_info_for_m2_slots(size_t num_of_entry, BL_HSIO_INFORMATION *config)
13 {
14  uint32_t reg32;
15  bool m2a_pcie, m2b_pcie;
16  uint8_t entry;
17  BL_FIA_MUX_CONFIG_HOB *fiamux_hob_data = get_fiamux_hob_data();
18  uint16_t supported_hsio_lanes;
19  void *spibar = fast_spi_get_bar();
20  uint32_t hsfs;
21 
22  /* Configure FIA MUX PCD */
23  supported_hsio_lanes =
24  (uint16_t)fiamux_hob_data->FiaMuxConfig.SkuNumLanesAllowed;
25 
26  /* Detects modules type */
27  // _GPIO_4 : LFFF: M2A_CFGn : M2A_SATAn : 0 SATA, 1 PCIe
29  m2a_pcie = (reg32 & B_PCH_GPIO_RX_STATE) ? 1 : 0;
30  // _GPIO_5 : LFFF: M2A_CFGn : M2A_SATAn : 0 SATA, 1 PCIe
32  m2b_pcie = (reg32 & B_PCH_GPIO_RX_STATE) ? 1 : 0;
33 
35  "GPIO values from M2 slots A:%d B:%d "
36  "(0=SATA, 1=PCIe or not populated)\n",
37  m2a_pcie, m2b_pcie);
38 
39  // HSIO default config is for PCIe, only update for SATA
40  // (also secondary PCIe lines are already set depending on SKU)
41  for (entry = 0; entry < num_of_entry; entry++) {
42  /* only update the active config */
43  if (config[entry].NumLanesSupported != supported_hsio_lanes)
44  continue;
45  BL_ME_FIA_CONFIG *fia_config = &(config[entry].FiaConfig);
46  BL_ME_FIA_MUX_CONFIG *mux_config =
47  &(config[entry].FiaConfig.MuxConfiguration);
48  BL_ME_FIA_SATA_CONFIG *sata_config =
49  &(config[entry].FiaConfig.SataLaneConfiguration);
50  if (!m2a_pcie) {
51  // change Lane 14 config
52  mux_config->BL_MeFiaMuxLaneMuxSel.Lane14MuxSel =
53  BL_ME_FIA_MUX_LANE_SATA;
54  sata_config->BL_MeFiaSataLaneSataSel.Lane14SataSel =
55  BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED;
56  }
57  if (!m2b_pcie) {
58  // change Lane 12 config
59  mux_config->BL_MeFiaMuxLaneMuxSel.Lane12MuxSel =
60  BL_ME_FIA_MUX_LANE_SATA;
61  sata_config->BL_MeFiaSataLaneSataSel.Lane12SataSel =
62  BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED;
63  }
64 
65  /* Check SPIBAR for security override
66  at least one M2 slot is populated with SATA
67  the configuration is different form ME current one */
69  if ((!(hsfs & SPIBAR_HSFSTS_FDOPSS))
70  && (!m2a_pcie || !m2b_pcie)
71  && memcmp(fia_config,
72  &fiamux_hob_data->FiaMuxConfig.FiaMuxConfig,
73  sizeof(BL_ME_FIA_CONFIG))) {
74  /* update configuration to NOT change ME config
75  as it will fail with security override set. */
76  memcpy(fia_config,
77  &fiamux_hob_data->FiaMuxConfig.FiaMuxConfig,
78  sizeof(BL_ME_FIA_CONFIG));
79  printk(BIOS_CRIT, "FLASH SECURITY OVERRIDE SET: "
80  "M2 SATA Slots are not available!\n");
81 
82  }
83  }
84 }
85 #endif
86 
87 size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config)
88 {
89  size_t num;
91 #ifdef __RAMSTAGE__
92  update_hsio_info_for_m2_slots(num, tagada_hsio_config);
93 #endif
94  (*p_hsio_config) = (BL_HSIO_INFORMATION *)tagada_hsio_config;
95  return num;
96 }
static uint32_t read32(const void *addr)
Definition: mmio.h:22
void * memcpy(void *dest, const void *src, size_t n)
Definition: memcpy.c:7
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define printk(level,...)
Definition: stdlib.h:16
#define PCH_PCR_ADDRESS(Pid, Offset)
Definition: pcr.h:10
void * fast_spi_get_bar(void)
Definition: fast_spi.c:24
#define SPIBAR_HSFSTS_FDOPSS
Definition: fast_spi_def.h:66
#define SPIBAR_HSFSTS_CTL
Definition: fast_spi_def.h:28
BL_FIA_MUX_CONFIG_HOB * get_fiamux_hob_data(void)
Definition: fiamux.c:103
size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config)
Definition: hsio.c:7
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
#define BIOS_CRIT
BIOS_CRIT - Recovery unlikely.
Definition: loglevel.h:56
enum board_config config
Definition: memory.c:448
#define PID_GPIO_4
Definition: gpio_defs.h:16
#define R_PAD_CFG_DW0_GPIO_5
Definition: gpio_defs.h:20
#define R_PAD_CFG_DW0_GPIO_4
Definition: gpio_defs.h:15
#define PID_GPIO_5
Definition: gpio_defs.h:21
DEVTREE_CONST BL_HSIO_INFORMATION tagada_hsio_config[]
Definition: hsio.h:9
#define B_PCH_GPIO_RX_STATE
Definition: gpio_defs.h:212
static uintptr_t spibar
Definition: spi.c:32
unsigned short uint16_t
Definition: stdint.h:11
unsigned int uint32_t
Definition: stdint.h:14
unsigned char uint8_t
Definition: stdint.h:8
int memcmp(const void *s1, const void *s2, size_t n)
Definition: memcmp.c:3