coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
smihandler.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
acpi/acpi.h
>
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#include <arch/io.h>
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#include <
cpu/x86/smm.h
>
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#include <soc/nvs.h>
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#include <
southbridge/intel/lynxpoint/pch.h
>
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#include <
southbridge/intel/lynxpoint/me.h
>
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#include <
northbridge/intel/haswell/haswell.h
>
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#include <
cpu/intel/haswell/haswell.h
>
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/*
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* Change LED_POWER# (SIO GPIO 45) state based on sleep type.
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* The IO address is hardcoded as we don't have device path in SMM.
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*/
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#define SIO_GPIO_BASE_SET4 (0x730 + 3)
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#define SIO_GPIO_BLINK_GPIO45 0x25
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void
mainboard_smi_sleep
(
u8
slp_typ)
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{
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u8
reg8;
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switch
(slp_typ) {
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case
ACPI_S3
:
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case
ACPI_S4
:
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break
;
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case
ACPI_S5
:
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/* Turn off LED */
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reg8 =
inb
(
SIO_GPIO_BASE_SET4
);
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reg8 |= (1 << 5);
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outb
(reg8,
SIO_GPIO_BASE_SET4
);
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break
;
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}
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}
haswell.h
mainboard_smi_sleep
void __weak mainboard_smi_sleep(u8 slp_typ)
Definition:
smihandler.c:210
inb
u8 inb(u16 port)
outb
void outb(u8 val, u16 port)
acpi.h
ACPI_S5
@ ACPI_S5
Definition:
acpi.h:1385
ACPI_S4
@ ACPI_S4
Definition:
acpi.h:1384
ACPI_S3
@ ACPI_S3
Definition:
acpi.h:1383
smm.h
SIO_GPIO_BASE_SET4
#define SIO_GPIO_BASE_SET4
Definition:
smihandler.c:16
haswell.h
me.h
pch.h
u8
uint8_t u8
Definition:
stdint.h:45
src
mainboard
intel
baskingridge
smihandler.c
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