coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
chromeos.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <bootmode.h>
4 #include <boot/coreboot_tables.h>
5 #include <device/pci_ops.h>
6 #include <console/console.h>
7 #include <device/device.h>
8 
11 #include <types.h>
12 #include <vendorcode/google/chromeos/chromeos.h>
13 #include "ec.h"
14 #include <ec/quanta/it8518/ec.h>
15 #include "onboard.h"
16 
17 void fill_lb_gpios(struct lb_gpios *gpios)
18 {
19  struct lb_gpio chromeos_gpios[] = {
20  /* Lid Switch: Virtual switch */
21  {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
22 
23  /* Power Button: Virtual switch */
24  /* Hard-code value to de-asserted */
25  {-1, ACTIVE_HIGH, 0, "power"},
26 
27  /* Was VGA Option ROM loaded? */
28  /* -1 indicates that this is a pseudo GPIO */
29  {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
30 
31  /* EC is in RW mode when it isn't in recovery mode. */
32  {-1, ACTIVE_HIGH, !get_recovery_mode_switch(), "ec_in_rw"}
33  };
34  lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
35 }
36 
38 {
39  return !get_gpio(GPIO_SPI_WP);
40 }
41 
42 int get_lid_switch(void)
43 {
44  /* hard-code to open */
45  return 1;
46 }
47 
48 /*
49  * The recovery-switch is virtual on Stout and is handled via the EC.
50  * Stout recovery mode is only valid if RTC_PWR_STS is set and the EC
51  * indicated the recovery keys were pressed. We use a global flag for
52  * rec_mode to be used after RTC_POWER_STS has been cleared.
53  * Note, rec_mode is the only time the EC is in RO mode, otherwise, RW.
54  */
56 {
57  static int ec_in_rec_mode;
58  static int ec_rec_flag_good;
59 
60  if (ec_rec_flag_good)
61  return ec_in_rec_mode;
62 
63  const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
64  u8 reg8 = pci_s_read_config8(dev, GEN_PMCON_3);
65 
67 
68  printk(BIOS_SPEW,"%s: EC status:%#x RTC_BAT: %x\n",
69  __func__, ec_status, reg8 & RTC_BATTERY_DEAD);
70 
71  ec_in_rec_mode = (((reg8 & RTC_BATTERY_DEAD) != 0) &&
72  ((ec_status & 0x3) == EC_IN_RECOVERY_MODE));
73  ec_rec_flag_good = 1;
74  return ec_in_rec_mode;
75 }
76 
77 static const struct cros_gpio cros_gpios[] = {
78  CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
79  CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
80 };
81 
void fill_lb_gpios(struct lb_gpios *gpios)
Definition: chromeos.c:9
int get_write_protect_state(void)
Only used if CONFIG(CHROMEOS) is set.
Definition: chromeos.c:15
int gfx_get_init_done(void)
Definition: bootmode.c:10
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define printk(level,...)
Definition: stdlib.h:16
u8 ec_read(u8 addr)
Definition: ec.c:107
#define EC_STATUS_REG
Definition: ec.h:57
#define EC_IN_RECOVERY_MODE
Definition: ec.h:65
ec_status
Definition: ec_commands.h:620
DECLARE_CROS_GPIOS(cros_gpios)
int get_recovery_mode_switch(void)
HACK: Use Fn-Key as recovery mode switch.
Definition: chromeos.c:29
#define GPIO_SPI_WP
Definition: onboard.h:23
int get_lid_switch(void)
Definition: chromeos.c:37
#define ACTIVE_HIGH
Definition: chromeos.c:18
static const struct cros_gpio cros_gpios[]
Definition: chromeos.c:77
int get_gpio(int community_base, int pad0_offset)
Definition: gpio_support.c:148
void lb_add_gpios(struct lb_gpios *gpios, const struct lb_gpio *gpio_table, size_t count)
#define RTC_BATTERY_DEAD
Definition: pmc.h:61
#define BIOS_SPEW
BIOS_SPEW - Excessively verbose output.
Definition: loglevel.h:142
static __always_inline uint8_t pci_s_read_config8(pci_devfn_t dev, uint16_t reg)
Definition: pci_io_cfg.h:80
#define PCI_DEV(SEGBUS, DEV, FN)
Definition: pci_type.h:14
u32 pci_devfn_t
Definition: pci_type.h:8
#define CROS_GPIO_DEVICE_NAME
Definition: gpio.h:14
#define GEN_PMCON_3
Definition: lpc.h:63
uint8_t u8
Definition: stdint.h:45