coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
finalize.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on Intel Tiger Lake Processor PCH Datasheet
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* Document number: 575857
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* Chapter number: 4, 29
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*/
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#include <
bootstate.h
>
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#include <
commonlib/console/post_codes.h
>
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#include <
console/console.h
>
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#include <
cpu/x86/smm.h
>
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#include <
device/mmio.h
>
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#include <
device/pci.h
>
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#include <
intelblocks/cse.h
>
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#include <
intelblocks/lpc_lib.h
>
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#include <
intelblocks/pcr.h
>
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#include <
intelblocks/pmclib.h
>
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#include <
intelblocks/systemagent.h
>
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#include <
intelblocks/tco.h
>
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#include <soc/p2sb.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <soc/smbus.h>
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#include <soc/soc_chip.h>
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#include <soc/systemagent.h>
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#include <
spi-generic.h
>
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static
void
pch_finalize
(
void
)
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{
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/* TCO Lock down */
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tco_lockdown
();
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/* TODO: Add Thermal Configuration */
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pmc_clear_pmcon_sts
();
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}
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static
void
tbt_finalize
(
void
)
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{
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int
i;
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const
struct
device
*dev;
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/* Disable Thunderbolt PCIe root ports bus master */
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for
(i = 0; i <
NUM_TBT_FUNCTIONS
; i++) {
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dev =
pcidev_path_on_root
(
SA_DEVFN_TBT
(i));
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if
(dev)
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pci_dev_disable_bus_master
(dev);
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}
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}
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static
void
soc_finalize
(
void
*unused)
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{
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printk
(
BIOS_DEBUG
,
"Finalizing chipset.\n"
);
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pch_finalize
();
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apm_control
(
APM_CNT_FINALIZE
);
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tbt_finalize
();
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if
(
CONFIG
(DISABLE_HECI1_AT_PRE_BOOT))
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heci1_disable
();
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/* Indicate finalize step with post code */
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post_code
(
POST_OS_BOOT
);
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}
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BOOT_STATE_INIT_ENTRY
(
BS_OS_RESUME
,
BS_ON_ENTRY
,
soc_finalize
,
NULL
);
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BOOT_STATE_INIT_ENTRY
(
BS_PAYLOAD_LOAD
,
BS_ON_EXIT
,
soc_finalize
,
NULL
);
bootstate.h
BS_PAYLOAD_LOAD
@ BS_PAYLOAD_LOAD
Definition:
bootstate.h:88
BS_OS_RESUME
@ BS_OS_RESUME
Definition:
bootstate.h:86
BS_ON_ENTRY
@ BS_ON_ENTRY
Definition:
bootstate.h:95
BS_ON_EXIT
@ BS_ON_EXIT
Definition:
bootstate.h:96
pcr.h
systemagent.h
printk
#define printk(level,...)
Definition:
stdlib.h:16
console.h
cse.h
pcidev_path_on_root
DEVTREE_CONST struct device * pcidev_path_on_root(pci_devfn_t devfn)
Definition:
device_const.c:255
heci1_disable
void heci1_disable(void)
Definition:
disable_heci.c:84
CONFIG
@ CONFIG
Definition:
dsi_common.h:201
smm.h
APM_CNT_FINALIZE
#define APM_CNT_FINALIZE
Definition:
smm.h:24
mmio.h
BIOS_DEBUG
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition:
loglevel.h:128
lpc_lib.h
pci.h
pci_dev_disable_bus_master
void pci_dev_disable_bus_master(const struct device *dev)
Definition:
pci_device.c:1616
post_code
#define post_code(value)
Definition:
post_code.h:12
post_codes.h
POST_OS_BOOT
#define POST_OS_BOOT
Final code before OS boots.
Definition:
post_codes.h:414
apm_control
int apm_control(u8 cmd)
Definition:
smi_trigger.c:31
BOOT_STATE_INIT_ENTRY
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL)
SA_DEVFN_TBT
#define SA_DEVFN_TBT(x)
Definition:
pci_devs.h:48
NUM_TBT_FUNCTIONS
#define NUM_TBT_FUNCTIONS
Definition:
pci_devs.h:49
pmclib.h
pmc_clear_pmcon_sts
void pmc_clear_pmcon_sts(void)
tco.h
tco_lockdown
void tco_lockdown(void)
Definition:
tco.c:50
soc_finalize
static void soc_finalize(void *unused)
Definition:
finalize.c:53
pch_finalize
static void pch_finalize(void)
Definition:
finalize.c:30
tbt_finalize
static void tbt_finalize(void)
Definition:
finalize.c:40
spi-generic.h
NULL
#define NULL
Definition:
stddef.h:19
device
Definition:
device.h:107
src
soc
intel
tigerlake
finalize.c
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