coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
cse.h File Reference
#include <types.h>
#include <vb2_api.h>
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Data Structures

struct  mkhi_hdr
 
struct  fw_version
 
struct  me_version
 
struct  me_fw_ver_resp
 
struct  cse_boot_perf_rsp
 

Macros

#define MKHI_GROUP_ID_CBM   0x0
 
#define MKHI_GROUP_ID_HMRFPO   0x5
 
#define MKHI_GROUP_ID_GEN   0xff
 
#define MKHI_GROUP_ID_BUP_COMMON   0xf0
 
#define MKHI_GROUP_ID_FWCAPS   0x3
 
#define MKHI_CBM_GLOBAL_RESET_REQ   0xb
 
#define MKHI_SET_ME_DISABLE   0x3
 
#define MKHI_SET_ME_ENABLE   0x3
 
#define GR_ORIGIN_BIOS_POST   0x2
 
#define MKHI_HMRFPO_ENABLE   0x1
 
#define MKHI_HMRFPO_GET_STATUS   0x3
 
#define MKHI_GEN_GET_FW_VERSION   0x2
 
#define MEI_BUS_DISABLE_COMMAND   0xc
 
#define MKHI_END_OF_POST   0xc
 
#define MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO   0x1c
 
#define MKHI_BUP_COMMON_SET_BOOT_PARTITION_INFO   0x1d
 
#define MKHI_BUP_COMMON_DATA_CLEAR   0x20
 
#define MKHI_BUP_COMMON_GET_BOOT_PERF_DATA   0x8
 
#define ME_HFS1_CWS_NORMAL   0x5
 
#define ME_HFS1_COM_NORMAL   0x0
 
#define ME_HFS1_COM_SOFT_TEMP_DISABLE   0x3
 
#define ME_HFS1_COM_SECOVER_MEI_MSG   0x5
 
#define ME_DISABLE_RULE_ID   6
 
#define ME_DISABLE_RULE_LENGTH   4
 
#define ME_DISABLE_COMMAND   0
 
#define ME_DISABLE_ATTEMPTS   3
 
#define ME_HFS3_FW_SKU_CONSUMER   0x2
 
#define ME_HFS3_FW_SKU_CORPORATE   0x3
 
#define ME_HFS3_FW_SKU_LITE   0x5
 
#define NUM_CSE_BOOT_PERF_DATA   64
 
#define BIOS_HOST_ADDR   0x00
 
#define HECI_MKHI_ADDR   0x07
 
#define HECI_MEI_ADDR   0x00
 
#define MKHI_HMRFPO_DISABLED   0
 
#define MKHI_HMRFPO_LOCKED   1
 
#define MKHI_HMRFPO_ENABLED   2
 

Enumerations

enum  {
  PCI_ME_HFSTS1 = 0x40 , PCI_ME_HFSTS2 = 0x48 , PCI_ME_HFSTS3 = 0x60 , PCI_ME_HFSTS4 = 0x64 ,
  PCI_ME_HFSTS5 = 0x68 , PCI_ME_HFSTS6 = 0x6C
}
 
enum  cse_tx_rx_status {
  CSE_TX_RX_SUCCESS = 0 , CSE_TX_ERR_TIMEOUT = 1 , CSE_RX_ERR_TIMEOUT = 2 , CSE_RX_ERR_RESP_LEN_MISMATCH = 3 ,
  CSE_TX_ERR_CSE_NOT_READY = 4 , CSE_RX_ERR_CSE_NOT_READY = 5 , CSE_TX_ERR_INPUT = 6 , CSE_RX_ERR_INPUT = 7
}
 
enum  csme_failure_reason {
  CSE_NO_ERROR = 0 , CSE_ERROR_UNSPECIFIED = 1 , CSE_LITE_SKU_RW_JUMP_ERROR = 2 , CSE_LITE_SKU_RW_ACCESS_ERROR = 3 ,
  CSE_LITE_SKU_RW_SWITCH_ERROR = 4 , CSE_LITE_SKU_FW_UPDATE_ERROR = 5 , CSE_COMMUNICATION_ERROR = 6 , CSE_LITE_SKU_DATA_WIPE_ERROR = 7 ,
  CSE_LITE_SKU_RW_BLOB_NOT_FOUND = 8 , CSE_LITE_SKU_RW_BLOB_SHA256_MISMATCH = 9 , CSE_LITE_SKU_RW_METADATA_NOT_FOUND = 10 , CSE_LITE_SKU_LAYOUT_MISMATCH_ERROR = 11 ,
  CSE_EOP_FAIL = 12 , CSE_LITE_SKU_SUB_PART_UPDATE_FAIL = 13 , CSE_LITE_SKU_SUB_PART_ACCESS_ERR = 14 , CSE_LITE_SKU_SUB_PART_BLOB_ACCESS_ERR = 15 ,
  CSE_LITE_SKU_SUB_PART_UPDATE_NOT_REQ = 16 , CSE_LITE_SKU_SUB_PART_LAYOUT_MISMATCH_ERROR = 17 , CSE_LITE_SKU_PART_UPDATE_SUCCESS = 18
}
 
enum  cse_boot_perf_data {
  PERF_DATA_CSME_ROM_START = 0 , PERF_DATA_EC_BOOT_LOAD_DONE = 1 , PERF_DATA_CSME_ROM_COMPLETED = 2 , PERF_DATA_CSME_GOT_ESE_INIT_DONE = 3 ,
  PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_START = 4 , PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_COMPLETED = 5 , PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC = 6 , PERF_DATA_CSME_POLL_FOR_PMC_PPS_START = 7 ,
  PERF_DATA_PMC_SET_PPS = 8 , PERF_DATA_CSME_BUP_START = 9 , PERF_DATA_CSME_HOST_BOOT_PREP_DONE = 10 , PERF_DATA_CSME_PHY_LOADING_START = 11 ,
  PERF_DATA_CSME_PHY_LOADING_COMPLETED = 12 , PERF_DATA_PMC_PWRGOOD_ASSERTED = 13 , PERF_DATA_PMC_SYS_PWROK_ASSERTED = 14 , PERF_DATA_PMC_CPU_BOOT_CONFIG_START = 15 ,
  PERF_DATA_CSME_CPU_BOOT_CONFIG_DONW = 16 , PERF_DATA_PMC_PLTRST_DEASSERTED = 17 , PERF_DATA_PMC_TC0_S0_ASSERTED = 18 , PERF_DATA_PMC_SENT_CRDA = 19 ,
  PERF_DATA_ACM_START = 20 , PERF_DATA_ACM_DONE = 21 , PERF_DATA_BIOS_DRAM_INIT_DONE = 22 , PERF_DATA_CSME_DRAM_INIT_DONE = 23 ,
  PERF_DATA_CSME_LOAD_TCSS_COMPLETED = 24 , PERF_DATA_PERF_DATA_CSME_LOAD_ISH_BRINGUP_START = 25 , PERF_DATA_CSME_LOAD_ISH_BRINGUP_DONE = 26 , PERF_DATA_CSME_LOAD_ISH_MAIN_START = 27 ,
  PERF_DATA_CSME_LOAD_ISH_MAIN_DONE = 28 , PERF_DATA_BIOS_END_OF_POST = 29 , PERF_DATA_CSME_END_OF_POST = 30 , PERF_DATA_BIOS_BIOS_CORE_DONE = 31 ,
  PERF_DATA_CSME_BIOS_CORE_DONE = 32 , PERF_DATA_CSME_GW_INIT_DONE = 33 , PERF_DATA_CSME_GET_PERF_RESPONSE = 63
}
 
enum  rst_req_type { GLOBAL_RESET = 1 , CSE_RESET_ONLY = 3 }
 
enum  cse_device_state { DEV_IDLE , DEV_ACTIVE }
 

Functions

void heci_init (uintptr_t bar)
 
enum cse_tx_rx_status heci_send_receive (const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz, uint8_t cse_addr)
 
int heci_reset (void)
 
void heci1_disable (void)
 
uint32_t me_read_config32 (int offset)
 
bool is_cse_devfn_visible (unsigned int devfn)
 
bool is_cse_enabled (void)
 
void cse_set_host_ready (void)
 
uint8_t cse_wait_sec_override_mode (void)
 
int cse_request_global_reset (void)
 
int cse_hmrfpo_enable (void)
 
int cse_hmrfpo_get_status (void)
 
void print_me_fw_version (void *unused)
 
enum cb_err get_me_fw_version (struct me_fw_ver_resp *resp)
 
bool cse_is_hfs1_cws_normal (void)
 
bool cse_is_hfs1_com_normal (void)
 
bool cse_is_hfs1_com_secover_mei_msg (void)
 
bool cse_is_hfs1_com_soft_temp_disable (void)
 
bool cse_is_hfs1_spi_protected (void)
 
bool cse_is_hfs3_fw_sku_lite (void)
 
uint8_t cse_wait_com_soft_temp_disable (void)
 
void cse_fw_sync (void)
 
void cse_board_reset (void)
 
void cse_trigger_vboot_recovery (enum csme_failure_reason reason)
 
enum cse_device_state get_cse_device_state (unsigned int devfn)
 
bool set_cse_device_state (unsigned int devfn, enum cse_device_state requested_state)
 
bool skip_cse_sub_part_update (void)
 
bool cse_get_boot_performance_data (struct cse_boot_perf_rsp *boot_perf)
 
bool cse_disable_mei_devices (void)
 
void cse_set_to_d0i3 (void)
 
void heci_set_to_d0i3 (void)
 
void cse_control_global_reset_lock (void)
 
void cse_send_end_of_post (void)
 
void soc_disable_heci1_using_pcr (void)
 
void cse_get_telemetry_data (void)
 

Variables

struct mkhi_hdr __packed
 

Macro Definition Documentation

◆ BIOS_HOST_ADDR

#define BIOS_HOST_ADDR   0x00

Definition at line 411 of file cse.h.

◆ GR_ORIGIN_BIOS_POST

#define GR_ORIGIN_BIOS_POST   0x2

Definition at line 24 of file cse.h.

◆ HECI_MEI_ADDR

#define HECI_MEI_ADDR   0x00

Definition at line 417 of file cse.h.

◆ HECI_MKHI_ADDR

#define HECI_MKHI_ADDR   0x07

Definition at line 414 of file cse.h.

◆ ME_DISABLE_ATTEMPTS

#define ME_DISABLE_ATTEMPTS   3

Definition at line 59 of file cse.h.

◆ ME_DISABLE_COMMAND

#define ME_DISABLE_COMMAND   0

Definition at line 58 of file cse.h.

◆ ME_DISABLE_RULE_ID

#define ME_DISABLE_RULE_ID   6

Definition at line 56 of file cse.h.

◆ ME_DISABLE_RULE_LENGTH

#define ME_DISABLE_RULE_LENGTH   4

Definition at line 57 of file cse.h.

◆ ME_HFS1_COM_NORMAL

#define ME_HFS1_COM_NORMAL   0x0

Definition at line 51 of file cse.h.

◆ ME_HFS1_COM_SECOVER_MEI_MSG

#define ME_HFS1_COM_SECOVER_MEI_MSG   0x5

Definition at line 53 of file cse.h.

◆ ME_HFS1_COM_SOFT_TEMP_DISABLE

#define ME_HFS1_COM_SOFT_TEMP_DISABLE   0x3

Definition at line 52 of file cse.h.

◆ ME_HFS1_CWS_NORMAL

#define ME_HFS1_CWS_NORMAL   0x5

Definition at line 48 of file cse.h.

◆ ME_HFS3_FW_SKU_CONSUMER

#define ME_HFS3_FW_SKU_CONSUMER   0x2

Definition at line 62 of file cse.h.

◆ ME_HFS3_FW_SKU_CORPORATE

#define ME_HFS3_FW_SKU_CORPORATE   0x3

Definition at line 63 of file cse.h.

◆ ME_HFS3_FW_SKU_LITE

#define ME_HFS3_FW_SKU_LITE   0x5

Definition at line 64 of file cse.h.

◆ MEI_BUS_DISABLE_COMMAND

#define MEI_BUS_DISABLE_COMMAND   0xc

Definition at line 34 of file cse.h.

◆ MKHI_BUP_COMMON_DATA_CLEAR

#define MKHI_BUP_COMMON_DATA_CLEAR   0x20

Definition at line 42 of file cse.h.

◆ MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO

#define MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO   0x1c

Definition at line 40 of file cse.h.

◆ MKHI_BUP_COMMON_GET_BOOT_PERF_DATA

#define MKHI_BUP_COMMON_GET_BOOT_PERF_DATA   0x8

Definition at line 45 of file cse.h.

◆ MKHI_BUP_COMMON_SET_BOOT_PARTITION_INFO

#define MKHI_BUP_COMMON_SET_BOOT_PARTITION_INFO   0x1d

Definition at line 41 of file cse.h.

◆ MKHI_CBM_GLOBAL_RESET_REQ

#define MKHI_CBM_GLOBAL_RESET_REQ   0xb

Definition at line 17 of file cse.h.

◆ MKHI_END_OF_POST

#define MKHI_END_OF_POST   0xc

Definition at line 37 of file cse.h.

◆ MKHI_GEN_GET_FW_VERSION

#define MKHI_GEN_GET_FW_VERSION   0x2

Definition at line 31 of file cse.h.

◆ MKHI_GROUP_ID_BUP_COMMON

#define MKHI_GROUP_ID_BUP_COMMON   0xf0

Definition at line 13 of file cse.h.

◆ MKHI_GROUP_ID_CBM

#define MKHI_GROUP_ID_CBM   0x0

Definition at line 10 of file cse.h.

◆ MKHI_GROUP_ID_FWCAPS

#define MKHI_GROUP_ID_FWCAPS   0x3

Definition at line 14 of file cse.h.

◆ MKHI_GROUP_ID_GEN

#define MKHI_GROUP_ID_GEN   0xff

Definition at line 12 of file cse.h.

◆ MKHI_GROUP_ID_HMRFPO

#define MKHI_GROUP_ID_HMRFPO   0x5

Definition at line 11 of file cse.h.

◆ MKHI_HMRFPO_DISABLED

#define MKHI_HMRFPO_DISABLED   0

Definition at line 421 of file cse.h.

◆ MKHI_HMRFPO_ENABLE

#define MKHI_HMRFPO_ENABLE   0x1

Definition at line 27 of file cse.h.

◆ MKHI_HMRFPO_ENABLED

#define MKHI_HMRFPO_ENABLED   2

Definition at line 430 of file cse.h.

◆ MKHI_HMRFPO_GET_STATUS

#define MKHI_HMRFPO_GET_STATUS   0x3

Definition at line 28 of file cse.h.

◆ MKHI_HMRFPO_LOCKED

#define MKHI_HMRFPO_LOCKED   1

Definition at line 427 of file cse.h.

◆ MKHI_SET_ME_DISABLE

#define MKHI_SET_ME_DISABLE   0x3

Definition at line 20 of file cse.h.

◆ MKHI_SET_ME_ENABLE

#define MKHI_SET_ME_ENABLE   0x3

Definition at line 21 of file cse.h.

◆ NUM_CSE_BOOT_PERF_DATA

#define NUM_CSE_BOOT_PERF_DATA   64

Definition at line 67 of file cse.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
PCI_ME_HFSTS1 
PCI_ME_HFSTS2 
PCI_ME_HFSTS3 
PCI_ME_HFSTS4 
PCI_ME_HFSTS5 
PCI_ME_HFSTS6 

Definition at line 70 of file cse.h.

◆ cse_boot_perf_data

Enumerator
PERF_DATA_CSME_ROM_START 
PERF_DATA_EC_BOOT_LOAD_DONE 
PERF_DATA_CSME_ROM_COMPLETED 
PERF_DATA_CSME_GOT_ESE_INIT_DONE 
PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_START 
PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_COMPLETED 
PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC 
PERF_DATA_CSME_POLL_FOR_PMC_PPS_START 
PERF_DATA_PMC_SET_PPS 
PERF_DATA_CSME_BUP_START 
PERF_DATA_CSME_HOST_BOOT_PREP_DONE 
PERF_DATA_CSME_PHY_LOADING_START 
PERF_DATA_CSME_PHY_LOADING_COMPLETED 
PERF_DATA_PMC_PWRGOOD_ASSERTED 
PERF_DATA_PMC_SYS_PWROK_ASSERTED 
PERF_DATA_PMC_CPU_BOOT_CONFIG_START 
PERF_DATA_CSME_CPU_BOOT_CONFIG_DONW 
PERF_DATA_PMC_PLTRST_DEASSERTED 
PERF_DATA_PMC_TC0_S0_ASSERTED 
PERF_DATA_PMC_SENT_CRDA 
PERF_DATA_ACM_START 
PERF_DATA_ACM_DONE 
PERF_DATA_BIOS_DRAM_INIT_DONE 
PERF_DATA_CSME_DRAM_INIT_DONE 
PERF_DATA_CSME_LOAD_TCSS_COMPLETED 
PERF_DATA_PERF_DATA_CSME_LOAD_ISH_BRINGUP_START 
PERF_DATA_CSME_LOAD_ISH_BRINGUP_DONE 
PERF_DATA_CSME_LOAD_ISH_MAIN_START 
PERF_DATA_CSME_LOAD_ISH_MAIN_DONE 
PERF_DATA_BIOS_END_OF_POST 
PERF_DATA_CSME_END_OF_POST 
PERF_DATA_BIOS_BIOS_CORE_DONE 
PERF_DATA_CSME_BIOS_CORE_DONE 
PERF_DATA_CSME_GW_INIT_DONE 
PERF_DATA_CSME_GET_PERF_RESPONSE 

Definition at line 206 of file cse.h.

◆ cse_device_state

Enumerator
DEV_IDLE 
DEV_ACTIVE 

Definition at line 499 of file cse.h.

◆ cse_tx_rx_status

Enumerator
CSE_TX_RX_SUCCESS 
CSE_TX_ERR_TIMEOUT 
CSE_RX_ERR_TIMEOUT 
CSE_RX_ERR_RESP_LEN_MISMATCH 
CSE_TX_ERR_CSE_NOT_READY 
CSE_RX_ERR_CSE_NOT_READY 
CSE_TX_ERR_INPUT 
CSE_RX_ERR_INPUT 

Definition at line 113 of file cse.h.

◆ csme_failure_reason

Enumerator
CSE_NO_ERROR 
CSE_ERROR_UNSPECIFIED 
CSE_LITE_SKU_RW_JUMP_ERROR 
CSE_LITE_SKU_RW_ACCESS_ERROR 
CSE_LITE_SKU_RW_SWITCH_ERROR 
CSE_LITE_SKU_FW_UPDATE_ERROR 
CSE_COMMUNICATION_ERROR 
CSE_LITE_SKU_DATA_WIPE_ERROR 
CSE_LITE_SKU_RW_BLOB_NOT_FOUND 
CSE_LITE_SKU_RW_BLOB_SHA256_MISMATCH 
CSE_LITE_SKU_RW_METADATA_NOT_FOUND 
CSE_LITE_SKU_LAYOUT_MISMATCH_ERROR 
CSE_EOP_FAIL 
CSE_LITE_SKU_SUB_PART_UPDATE_FAIL 
CSE_LITE_SKU_SUB_PART_ACCESS_ERR 
CSE_LITE_SKU_SUB_PART_BLOB_ACCESS_ERR 
CSE_LITE_SKU_SUB_PART_UPDATE_NOT_REQ 
CSE_LITE_SKU_SUB_PART_LAYOUT_MISMATCH_ERROR 
CSE_LITE_SKU_PART_UPDATE_SUCCESS 

Definition at line 146 of file cse.h.

◆ rst_req_type

Enumerator
GLOBAL_RESET 
CSE_RESET_ONLY 

Definition at line 375 of file cse.h.

Function Documentation

◆ cse_board_reset()

void cse_board_reset ( void  )

Definition at line 350 of file cse_lite.c.

Referenced by cse_set_and_boot_from_next_bp().

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◆ cse_control_global_reset_lock()

void cse_control_global_reset_lock ( void  )

Definition at line 1023 of file cse.c.

References CONFIG, cse_is_hfs1_spi_protected(), pmc_global_reset_disable_and_lock(), and pmc_global_reset_enable().

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◆ cse_disable_mei_devices()

bool cse_disable_mei_devices ( void  )

Definition at line 31 of file disable_heci.c.

References BIOS_ERR, CB_SUCCESS, PMC_IPC_MEI_DISABLE_ID, PMC_IPC_MEI_DISABLE_SUBID_DISABLE, pmc_make_ipc_cmd(), pmc_send_ipc_cmd(), and printk.

Referenced by cse_handle_eop_error(), and heci1_disable_using_pmc().

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◆ cse_fw_sync()

void cse_fw_sync ( void  )

Definition at line 1042 of file cse_lite.c.

Referenced by mainboard_romstage_entry().

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◆ cse_get_boot_performance_data()

bool cse_get_boot_performance_data ( struct cse_boot_perf_rsp boot_perf)

Definition at line 133 of file cse_lite.c.

References __packed, BIOS_ERR, cse_boot_perf_rsp::hdr, HECI_MKHI_ADDR, heci_send_receive(), MKHI_BUP_COMMON_GET_BOOT_PERF_DATA, MKHI_GROUP_ID_BUP_COMMON, printk, and mkhi_hdr::result.

Referenced by cbmem_inject_telemetry_data().

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◆ cse_get_telemetry_data()

void cse_get_telemetry_data ( void  )

Definition at line 76 of file telemetry.c.

References BIOS_DEBUG, cbmem_inject_telemetry_data(), is_cse_enabled(), and printk.

Referenced by mainboard_romstage_entry().

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◆ cse_hmrfpo_enable()

int cse_hmrfpo_enable ( void  )

Definition at line 748 of file cse.c.

References __packed, BIOS_DEBUG, BIOS_ERR, cse_is_hfs1_com_secover_mei_msg(), cse_is_hmrfpo_enable_allowed(), HECI_MKHI_ADDR, heci_send_receive(), MKHI_GROUP_ID_HMRFPO, MKHI_HMRFPO_ENABLE, and printk.

Referenced by cse_prep_for_component_update(), and cse_prep_for_rw_update().

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◆ cse_hmrfpo_get_status()

int cse_hmrfpo_get_status ( void  )

Definition at line 812 of file cse.c.

References __packed, BIOS_ERR, BIOS_INFO, cse_is_hfs1_cws_normal(), HECI_MKHI_ADDR, heci_send_receive(), MKHI_GROUP_ID_HMRFPO, MKHI_HMRFPO_GET_STATUS, and printk.

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◆ cse_is_hfs1_com_normal()

bool cse_is_hfs1_com_normal ( void  )

Definition at line 250 of file cse.c.

References cse_check_hfs1_com(), and ME_HFS1_COM_NORMAL.

Referenced by cse_is_bp_cmd_info_possible(), cse_is_global_reset_allowed(), cse_is_hmrfpo_enable_allowed(), and platform_fsp_silicon_init_params_cb().

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◆ cse_is_hfs1_com_secover_mei_msg()

bool cse_is_hfs1_com_secover_mei_msg ( void  )

Definition at line 255 of file cse.c.

References cse_check_hfs1_com(), and ME_HFS1_COM_SECOVER_MEI_MSG.

Referenced by cse_hmrfpo_enable(), cse_is_bp_cmd_info_possible(), cse_is_global_reset_allowed(), and cse_wait_sec_override_mode().

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◆ cse_is_hfs1_com_soft_temp_disable()

bool cse_is_hfs1_com_soft_temp_disable ( void  )

Definition at line 260 of file cse.c.

References cse_check_hfs1_com(), and ME_HFS1_COM_SOFT_TEMP_DISABLE.

Referenced by cse_data_clear_request(), cse_is_bp_cmd_info_possible(), cse_is_global_reset_allowed(), cse_is_hmrfpo_enable_allowed(), and cse_wait_com_soft_temp_disable().

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◆ cse_is_hfs1_cws_normal()

bool cse_is_hfs1_cws_normal ( void  )

Definition at line 241 of file cse.c.

References me_hfsts1::data, me_hfsts1::fields, ME_HFS1_CWS_NORMAL, me_read_config32(), PCI_ME_HFSTS1, and me_hfsts1::working_state.

Referenced by cse_data_clear_request(), cse_hmrfpo_get_status(), cse_is_bp_cmd_info_possible(), cse_is_global_reset_allowed(), and cse_is_hmrfpo_enable_allowed().

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◆ cse_is_hfs1_spi_protected()

bool cse_is_hfs1_spi_protected ( void  )

Definition at line 274 of file cse.c.

References me_hfsts1::data, me_hfsts1::fields, me_read_config32(), me_hfsts1::mfg_mode, and PCI_ME_HFSTS1.

Referenced by cse_control_global_reset_lock().

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◆ cse_is_hfs3_fw_sku_lite()

bool cse_is_hfs3_fw_sku_lite ( void  )

Definition at line 281 of file cse.c.

References me_hfsts3::data, me_hfsts3::fields, me_hfsts3::fw_sku, ME_HFS3_FW_SKU_LITE, me_read_config32(), and PCI_ME_HFSTS3.

Referenced by cse_is_global_reset_allowed(), cse_is_hmrfpo_enable_allowed(), and platform_fsp_silicon_init_params_cb().

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◆ cse_request_global_reset()

int cse_request_global_reset ( void  )

Definition at line 722 of file cse.c.

References cse_request_reset(), and GLOBAL_RESET.

Referenced by do_global_reset(), and send_global_reset().

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◆ cse_send_end_of_post()

void cse_send_end_of_post ( void  )

Definition at line 236 of file cse_eop.c.

References do_send_end_of_post().

Referenced by soc_init_pre_device().

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◆ cse_set_host_ready()

void cse_set_host_ready ( void  )

Definition at line 289 of file cse.c.

References CSR_IG, CSR_READY, CSR_RESET, read_host_csr(), and write_host_csr().

Referenced by heci_reset().

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◆ cse_set_to_d0i3()

void cse_set_to_d0i3 ( void  )

Definition at line 1003 of file cse.c.

References DEV_IDLE, is_cse_devfn_visible(), PCH_DEVFN_CSE, and set_cse_device_state().

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◆ cse_trigger_vboot_recovery()

void cse_trigger_vboot_recovery ( enum csme_failure_reason  reason)

Definition at line 918 of file cse.c.

References BIOS_DEBUG, CONFIG, die(), me_read_config32(), NULL, PCI_ME_HFSTS1, PCI_ME_HFSTS2, PCI_ME_HFSTS3, printk, vboot_get_context(), vboot_reboot(), and vboot_save_data().

Referenced by cse_sub_part_fw_component_update(), and handle_cse_eop_result().

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◆ cse_wait_com_soft_temp_disable()

uint8_t cse_wait_com_soft_temp_disable ( void  )

◆ cse_wait_sec_override_mode()

uint8_t cse_wait_sec_override_mode ( void  )

◆ get_cse_device_state()

enum cse_device_state get_cse_device_state ( unsigned int  devfn)

Definition at line 954 of file cse.c.

Referenced by set_cse_device_state().

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◆ get_me_fw_version()

enum cb_err get_me_fw_version ( struct me_fw_ver_resp resp)

◆ heci1_disable()

void heci1_disable ( void  )

Definition at line 84 of file disable_heci.c.

References BIOS_ERR, BIOS_INFO, CONFIG, ENV_SMM, heci1_disable_using_pcr(), heci1_disable_using_pmc(), heci1_disable_using_sbi(), and printk.

Referenced by heci_cse_lockdown(), heci_finalize(), pch_finalize_script(), smihandler_soc_at_finalize(), and soc_finalize().

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◆ heci_init()

void heci_init ( uintptr_t  bar)

Definition at line 92 of file cse.c.

References get_cse_bar(), HECI1_BASE_ADDRESS, heci_reset(), is_cse_enabled(), PCH_DEV_CSE, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_COMMAND, PCI_COMMAND_MASTER, PCI_COMMAND_MEMORY, pci_or_config16(), pci_read_config16(), pci_write_config16(), and pci_write_config32().

Referenced by mainboard_romstage_entry().

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◆ heci_reset()

int heci_reset ( void  )

Definition at line 599 of file cse.c.

References BIOS_CRIT, cse_set_host_ready(), CSR_IG, CSR_RESET, post_code, printk, read_host_csr(), wait_heci_ready(), and write_host_csr().

Referenced by cse_request_reset(), and heci_init().

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◆ heci_send_receive()

enum cse_tx_rx_status heci_send_receive ( const void snd_msg,
size_t  snd_sz,
void rcv_msg,
size_t rcv_sz,
uint8_t  cse_addr 
)

◆ heci_set_to_d0i3()

void heci_set_to_d0i3 ( void  )

Definition at line 1012 of file cse.c.

References DEV_IDLE, is_cse_devfn_visible(), PCH_DEV_SLOT_CSE, PCI_DEVFN, and set_cse_device_state().

Referenced by heci_finalize().

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◆ is_cse_devfn_visible()

bool is_cse_devfn_visible ( unsigned int  devfn)

Definition at line 622 of file cse.c.

References BIOS_WARNING, is_devfn_enabled(), PCI_DEV, PCI_FUNC, pci_read_config16(), PCI_SLOT, PCI_VENDOR_ID, and printk.

Referenced by cse_set_to_d0i3(), heci_set_to_d0i3(), and is_cse_enabled().

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◆ is_cse_enabled()

bool is_cse_enabled ( void  )

Definition at line 640 of file cse.c.

References is_cse_devfn_visible(), and PCH_DEVFN_CSE.

Referenced by cse_get_telemetry_data(), cse_request_reset(), do_send_end_of_post(), dump_cse_state(), dump_me_status(), heci_init(), intel_me_status(), and send_global_reset().

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◆ me_read_config32()

uint32_t me_read_config32 ( int  offset)

Definition at line 645 of file cse.c.

References offset, PCH_DEV_CSE, and pci_read_config32().

Referenced by cse_check_hfs1_com(), cse_is_hfs1_cws_normal(), cse_is_hfs1_spi_protected(), cse_is_hfs3_fw_sku_lite(), cse_trigger_vboot_recovery(), dump_me_status(), dump_status(), intel_me_status(), and send_global_reset().

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◆ print_me_fw_version()

void print_me_fw_version ( void unused)

Definition at line 855 of file cse.c.

◆ set_cse_device_state()

bool set_cse_device_state ( unsigned int  devfn,
enum cse_device_state  requested_state 
)

Definition at line 987 of file cse.c.

References DEV_ACTIVE, ensure_cse_active(), ensure_cse_idle(), get_cse_device_state(), PCI_DEV, PCI_FUNC, and PCI_SLOT.

Referenced by cse_set_to_d0i3(), do_send_end_of_post(), and heci_set_to_d0i3().

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◆ skip_cse_sub_part_update()

bool skip_cse_sub_part_update ( void  )

Definition at line 29 of file romstage.c.

References cpu_get_cpuid(), and CPUID_ALDERLAKE_K0.

Referenced by cse_sub_part_fw_update().

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◆ soc_disable_heci1_using_pcr()

void soc_disable_heci1_using_pcr ( void  )

Definition at line 195 of file cse.c.

References p2sb_disable_sideband_access(), p2sb_unhide(), pcr_or32(), PCR_PSFX_T0_SHDW_PCIEN, PCR_PSFX_T0_SHDW_PCIEN_FUNDIS, PID_PSF1, PID_PSF3, PSF3_BASE_ADDRESS, and PSF_BASE_ADDRESS.

Referenced by heci1_disable_using_pcr().

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Variable Documentation

◆ __packed