coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-only */
2
3
#include <soc/gpio.h>
4
#include <variant/gpio.h>
5
6
static
const
struct
pad_config
gpio_table
[] = {
7
/* GPP_A14 GPIO 0x0000002644000300 */
PAD_NC
(
GPP_A14
,
NONE
),
8
/* GPP_A16 GPIO 0x0000002444000300 */
PAD_NC
(
GPP_A16
, DN_20K),
9
/* GPP_B8 GPIO 0x0000003844000300 */
PAD_NC
(
GPP_B8
,
NONE
),
10
/* GPP_B14 SPKR 0x0000003e44000600 */
PAD_CFG_NF
(
GPP_B14
,
NONE
, DEEP, NF1),
11
/* GPP_B18 GPIO 0x0000004244000300 */
PAD_NC
(
GPP_B18
,
NONE
),
12
/* GPP_B22 GPIO 0x0000004644000300 */
PAD_NC
(
GPP_B22
,
NONE
),
13
/* GPP_C2 GPIO 0x0000004a44000300 */
PAD_NC
(
GPP_C2
,
NONE
),
14
/* GPP_C5 GPIO 0x0000004d44000300 */
PAD_NC
(
GPP_C5
,
NONE
),
15
/* GPP_C6 SML1CLK 0x0000004e44000703 */
PAD_CFG_NF
(
GPP_C6
,
NONE
, DEEP, NF1),
16
/* GPP_C7 SML1DATA 0x0000004f44000703 */
PAD_CFG_NF
(
GPP_C7
,
NONE
, DEEP, NF1),
17
/* GPP_C8 UART0A_RXD 0x0000005044000702 */
PAD_CFG_NF
(
GPP_C8
,
NONE
, DEEP, NF1),
18
/* GPP_C9 UART0A_TXD 0x0000005144000700 */
PAD_CFG_NF
(
GPP_C9
,
NONE
, DEEP, NF1),
19
/* GPP_C10 UART0A_RTS# 0x0000005244000700 */
PAD_CFG_NF
(
GPP_C10
,
NONE
, DEEP, NF1),
20
/* GPP_C11 UART0A_CTS# 0x0000005344000702 */
PAD_CFG_NF
(
GPP_C11
,
NONE
, DEEP, NF1),
21
/* GPP_C12 GPIO 0x0000005444000102 */
PAD_CFG_GPI
(
GPP_C12
,
NONE
, DEEP),
22
/* GPP_C13 GPIO 0x0000005544000102 */
PAD_CFG_GPI
(
GPP_C13
,
NONE
, DEEP),
23
/* GPP_C14 GPIO 0x0000005644000102 */
PAD_CFG_GPI
(
GPP_C14
,
NONE
, DEEP),
24
/* GPP_C15 GPIO 0x0000005744000100 */
PAD_CFG_GPI
(
GPP_C15
,
NONE
, DEEP),
25
/* GPP_C16 I2C0_SDA 0x0000005844000402 */
PAD_CFG_NF
(
GPP_C16
,
NONE
, DEEP, NF1),
26
/* GPP_C17 I2C0_SCL 0x0000005944000602 */
PAD_CFG_NF
(
GPP_C17
,
NONE
, DEEP, NF1),
27
/* GPP_C20 UART2_RXD 0x0000005c44000500 */
PAD_CFG_NF
(
GPP_C20
,
NONE
, DEEP, NF1),
28
/* GPP_C21 UART2_TXD 0x0000005d44000600 */
PAD_CFG_NF
(
GPP_C21
,
NONE
, DEEP, NF1),
29
/* GPP_C22 UART2_RTS# 0x0000005e44000500 */
PAD_CFG_NF
(
GPP_C22
,
NONE
, DEEP, NF1),
30
/* GPP_C23 UART2_CTS# 0x0000005f44000502 */
PAD_CFG_NF
(
GPP_C23
,
NONE
, DEEP, NF1),
31
/* GPP_D1 GPIO 0x0000006144000102 */
PAD_CFG_GPI
(
GPP_D1
,
NONE
, DEEP),
32
/* GPP_D2 GPIO 0x0000006244800102 */
PAD_CFG_GPI
(
GPP_D2
,
NONE
, DEEP),
33
/* GPP_D3 GPIO 0x0000006344000201 */
PAD_CFG_GPO
(
GPP_D3
, 1, DEEP),
34
/* GPP_D7 GPIO 0x0000006784000102 */
PAD_CFG_GPI
(
GPP_D7
,
NONE
, PLTRST),
35
/* GPP_D8 GPIO 0x0000006884000100 */
PAD_CFG_GPI
(
GPP_D8
,
NONE
, PLTRST),
36
/* GPP_D17 DMIC_CLK1 0x0000007144000700 */
PAD_CFG_NF
(
GPP_D17
,
NONE
, DEEP, NF1),
37
/* GPP_D18 DMIC_DATA1 0x0000007244000700 */
PAD_CFG_NF
(
GPP_D18
,
NONE
, DEEP, NF1),
38
/* GPP_D19 DMIC_CLK0 0x0000007344000700 */
PAD_CFG_NF
(
GPP_D19
,
NONE
, DEEP, NF1),
39
/* GPP_D20 DMIC_DATA0 0x0000007444000700 */
PAD_CFG_NF
(
GPP_D20
,
NONE
, DEEP, NF1),
40
/* GPP_D21 GPIO 0x0000007544000300 */
PAD_NC
(
GPP_D21
,
NONE
),
41
/* GPP_D22 GPIO 0x0000007644000300 */
PAD_NC
(
GPP_D22
,
NONE
),
42
/* GPP_G1 GPIO 0x0000006d44000300 */
PAD_NC
(
GPP_G1
,
NONE
),
43
/* GPP_G2 GPIO 0x0000006e44000300 */
PAD_NC
(
GPP_G2
,
NONE
),
44
/* GPP_G3 GPIO 0x0000006f40880102 */
PAD_CFG_GPI_APIC
(
GPP_G3
,
NONE
, DEEP, LEVEL, INVERT),
45
/* I2S1_SFRM GPIO 0x0000000040000300 */
PAD_NC
(
I2S1_SFRM
,
NONE
),
46
/* I2S1_TXD GPIO 0x0000000040000300 */
PAD_NC
(
I2S1_TXD
,
NONE
),
47
/* GPD0 BATLOW# 0x0000006044000702 */
PAD_CFG_NF
(
GPD0
,
NONE
, DEEP, NF1),
48
/* GPD1 ACPRESENT 0x00003c6144000502 */
PAD_CFG_NF
(
GPD1
, NATIVE, DEEP, NF1),
49
/* GPD7 GPIO 0x0000006704000200 */
PAD_NC
(
GPD7
, DN_20K),
/* unused, formerly USB always on */
50
/* GPD9 GPIO 0x0000006904000200 */
PAD_CFG_GPO
(
GPD9
, 0, PWROK),
51
/* GPD11 GPIO 0x0000006b04000200 */
PAD_CFG_GPO
(
GPD11
, 0, PWROK),
52
/* GPP_K0 GPIO 0x0000001884000102 */
PAD_CFG_GPI
(
GPP_K0
,
NONE
, PLTRST),
53
/* GPP_K1 GPIO 0x0000001984000100 */
PAD_CFG_GPI
(
GPP_K1
,
NONE
, PLTRST),
54
/* GPP_K2 GPIO 0x0000001a84000100 */
PAD_CFG_GPI
(
GPP_K2
,
NONE
, PLTRST),
55
/* GPP_K3 GPIO 0x0000001b84000102 */
PAD_CFG_GPI
(
GPP_K3
,
NONE
, PLTRST),
56
/* GPP_K4 GPIO 0x0000001c44000300 */
PAD_NC
(
GPP_K4
,
NONE
),
57
/* GPP_K5 GPIO 0x0000001d44000300 */
PAD_NC
(
GPP_K5
,
NONE
),
58
/* GPP_K8 GPIO 0x0000002044000300 */
PAD_NC
(
GPP_K8
,
NONE
),
59
/* GPP_K9 GPIO 0x0000002144000300 */
PAD_NC
(
GPP_K9
,
NONE
),
60
/* GPP_K10 GPIO 0x0000002244000300 */
PAD_NC
(
GPP_K10
,
NONE
),
61
/* GPP_K11 GPIO 0x0000002344000300 */
PAD_NC
(
GPP_K11
,
NONE
),
62
/* GPP_K20 GPIO 0x0000002c84000201 */
PAD_CFG_GPO
(
GPP_K20
, 1, PLTRST),
63
/* GPP_K21 GPIO 0x0000002d44000300 */
PAD_NC
(
GPP_K21
,
NONE
),
64
/* GPP_H0 GPIO 0x0000004844000300 */
PAD_NC
(
GPP_H0
,
NONE
),
65
/* GPP_H2 GPIO 0x0000004a44000300 */
PAD_NC
(
GPP_H2
,
NONE
),
66
/* GPP_H3 GPIO 0x0000004b44000300 */
PAD_NC
(
GPP_H3
,
NONE
),
67
/* GPP_H10 GPIO 0x0000005244000300 */
PAD_NC
(
GPP_H10
,
NONE
),
68
/* GPP_H15 GPIO 0x0000005744000300 */
PAD_NC
(
GPP_H15
,
NONE
),
69
/* GPP_H17 GPIO 0x0000005944000300 */
PAD_NC
(
GPP_H17
,
NONE
),
70
/* GPP_E0 SATAXPCIE0 0x0000001844800502 */
PAD_CFG_NF
(
GPP_E0
,
NONE
, DEEP, NF1),
71
/* GPP_E1 GPIO 0x0000001944000300 */
PAD_NC
(
GPP_E1
,
NONE
),
72
/* GPP_E2 GPIO 0x0000001a44000300 */
PAD_NC
(
GPP_E2
,
NONE
),
73
/* GPP_E4 SATA_DEVSLP0 0x0000001c44000600 */
PAD_CFG_NF
(
GPP_E4
,
NONE
, DEEP, NF1),
74
/* GPP_E5 GPIO 0x0000301d44800102 */
PAD_CFG_GPI
(
GPP_E5
,
NONE
, DEEP),
75
/* GPP_E6 GPIO 0x0000001e44800102 */
PAD_CFG_GPI
(
GPP_E6
,
NONE
, DEEP),
76
/* GPP_E8 SATALED# 0x0000002044000700 */
PAD_CFG_NF
(
GPP_E8
,
NONE
, DEEP, NF1),
77
/* GPP_E9 USB2_OC0# 0x0000302144000702 */
PAD_CFG_NF
(
GPP_E9
, UP_20K, DEEP, NF1),
78
/* GPP_E10 USB2_OC1# 0x0000302244000702 */
PAD_CFG_NF
(
GPP_E10
, UP_20K, DEEP, NF1),
79
/* GPP_E11 USB2_OC2# 0x0000302344000702 */
PAD_CFG_NF
(
GPP_E11
, UP_20K, DEEP, NF1),
80
/* GPP_E12 GPIO 0x0000002484000200 */
PAD_CFG_GPO
(
GPP_E12
, 0, PLTRST),
81
/* GPP_F1 GPIO 0x0000003144000300 */
PAD_NC
(
GPP_F1
,
NONE
),
82
/* GPP_F2 GPIO 0x0000003244000300 */
PAD_NC
(
GPP_F2
,
NONE
),
83
/* GPP_F3 GPIO 0x0000003344000300 */
PAD_NC
(
GPP_F3
,
NONE
),
84
/* GPP_F4 GPIO 0x0000003444000300 */
PAD_NC
(
GPP_F4
,
NONE
),
85
/* GPP_F5 GPIO 0x0000003544000300 */
PAD_NC
(
GPP_F5
,
NONE
),
86
/* GPP_F6 SATA_DEVSLP4 0x0000003644000700 */
PAD_CFG_NF
(
GPP_F6
,
NONE
, DEEP, NF1),
87
/* GPP_F8 GPIO 0x0000003844000300 */
PAD_NC
(
GPP_F8
,
NONE
),
88
/* GPP_F9 GPIO 0x0000003944000300 */
PAD_NC
(
GPP_F9
,
NONE
),
89
/* GPP_F10 GPIO 0x0000003a84000100 */
PAD_CFG_GPI
(
GPP_F10
,
NONE
, PLTRST),
90
/* GPP_F13 GPIO 0x0000003d82800102 */
PAD_CFG_GPI
(
GPP_F13
,
NONE
, PLTRST),
91
/* GPP_F14 GPIO 0x0000003e44000300 */
PAD_NC
(
GPP_F14
,
NONE
),
92
/* GPP_F15 USB2_OC4# 0x0000303f44000702 */
PAD_CFG_NF
(
GPP_F15
, UP_20K, DEEP, NF1),
93
/* GPP_F16 USB2_OC5# 0x0000304044000702 */
PAD_CFG_NF
(
GPP_F16
, UP_20K, DEEP, NF1),
94
/* GPP_F17 USB2_OC6# 0x0000304144000702 */
PAD_CFG_NF
(
GPP_F17
, UP_20K, DEEP, NF1),
95
/* GPP_F18 GPIO 0x0000004240880102 */
PAD_CFG_GPI_APIC
(
GPP_F18
,
NONE
, DEEP, LEVEL, INVERT),
96
/* GPP_F19 eDP_VDDEN 0x0000004344000700 */
PAD_CFG_NF
(
GPP_F19
,
NONE
, DEEP, NF1),
97
/* GPP_F20 eDP_BKLTEN 0x0000004444000700 */
PAD_CFG_NF
(
GPP_F20
,
NONE
, DEEP, NF1),
98
/* GPP_F21 eDP_BKLTCTL 0x0000004544000700 */
PAD_CFG_NF
(
GPP_F21
,
NONE
, DEEP, NF1),
99
/* GPP_F22 GPIO 0x0000004644000300 */
PAD_NC
(
GPP_F22
,
NONE
),
100
/* GPP_F23 GPIO 0x0000004744000300 */
PAD_NC
(
GPP_F23
,
NONE
),
101
/* GPP_I0 DDPB_HPD0 0x00003c0040000700 */
PAD_CFG_NF
(
GPP_I0
, NATIVE, DEEP, NF1),
102
/* GPP_I1 DDPB_HPD1 0x00003c0040000700 */
PAD_CFG_NF
(
GPP_I1
, NATIVE, DEEP, NF1),
103
/* GPP_I2 DDPB_HPD2 0x00003c0040000700 */
PAD_CFG_NF
(
GPP_I2
, NATIVE, DEEP, NF1),
104
/* GPP_I3 DDPB_HPD3 0x0000000040000700 */
PAD_CFG_NF
(
GPP_I3
,
NONE
, DEEP, NF1),
105
/* GPP_I4 EDP_HPD 0x0000000040000700 */
PAD_CFG_NF
(
GPP_I4
,
NONE
, DEEP, NF1),
106
/* GPP_I5 DDPB_CTRLCLK 0x0000000040000700 */
PAD_CFG_NF
(
GPP_I5
,
NONE
, DEEP, NF1),
107
/* GPP_I6 DDPB_CTRLDATA 0x0000000040000702 */
PAD_CFG_NF
(
GPP_I6
,
NONE
, DEEP, NF1),
108
/* GPP_I7 DDPC_CTRLCLK 0x0000000040000700 */
PAD_CFG_NF
(
GPP_I7
,
NONE
, DEEP, NF1),
109
/* GPP_I8 DDPC_CTRLDATA 0x0000000040000700 */
PAD_CFG_NF
(
GPP_I8
,
NONE
, DEEP, NF1),
110
/* GPP_I9 DDPD_CTRLCLK 0x0000100040000700 */
PAD_CFG_NF
(
GPP_I9
, DN_20K, DEEP, NF1),
111
/* GPP_I10 DDPD_CTRLDATA 0x0000100040000700 */
PAD_CFG_NF
(
GPP_I10
, DN_20K, DEEP, NF1),
112
/* GPP_J2 n/a 0x0000003044000700 */
PAD_CFG_NF
(
GPP_J2
,
NONE
, DEEP, NF1),
113
/* GPP_J3 n/a 0x0000003144000700 */
PAD_CFG_NF
(
GPP_J3
,
NONE
, DEEP, NF1),
114
/* GPP_J4 CNV_BRI_DT 0x0000003244000702 */
PAD_CFG_NF
(
GPP_J4
,
NONE
, DEEP, NF1),
115
/* GPP_J5 GPIO 0x0000003344000300 */
PAD_NC
(
GPP_J5
,
NONE
),
116
/* GPP_J6 CNV_RGI_DT 0x0000003444000700 */
PAD_CFG_NF
(
GPP_J6
,
NONE
, DEEP, NF1),
117
/* GPP_J7 CNV_RGI_RSP 0x0000003544000700 */
PAD_CFG_NF
(
GPP_J7
,
NONE
, DEEP, NF1),
118
/* GPP_J8 CNV_MFUART2_RXD 0x0000003644000602 */
PAD_CFG_NF
(
GPP_J8
,
NONE
, DEEP, NF1),
119
/* GPP_J9 CNV_MFUART2_TXD 0x0000003744000702 */
PAD_CFG_NF
(
GPP_J9
,
NONE
, DEEP, NF1),
120
/* GPP_J10 n/a 0x0000003844000602 */
PAD_CFG_NF
(
GPP_J10
,
NONE
, DEEP, NF1),
121
/* GPP_J11 A4WP_PRESENT 0x0000003944000700 */
PAD_CFG_NF
(
GPP_J11
,
NONE
, DEEP, NF1),
122
};
123
124
void
variant_configure_gpios
(
void
)
125
{
126
gpio_configure_pads
(
gpio_table
,
ARRAY_SIZE
(
gpio_table
));
127
}
GPD11
#define GPD11
Definition:
gpio_soc_defs.h:392
GPP_C15
#define GPP_C15
Definition:
gpio_soc_defs.h:552
GPP_D1
#define GPP_D1
Definition:
gpio_soc_defs.h:253
GPD9
#define GPD9
Definition:
gpio_soc_defs.h:390
GPP_C2
#define GPP_C2
Definition:
gpio_soc_defs.h:539
GPP_D8
#define GPP_D8
Definition:
gpio_soc_defs.h:260
GPP_D17
#define GPP_D17
Definition:
gpio_soc_defs.h:269
GPP_F21
#define GPP_F21
Definition:
gpio_soc_defs.h:594
GPP_C12
#define GPP_C12
Definition:
gpio_soc_defs.h:549
GPP_F16
#define GPP_F16
Definition:
gpio_soc_defs.h:589
GPP_H15
#define GPP_H15
Definition:
gpio_soc_defs.h:231
GPP_E0
#define GPP_E0
Definition:
gpio_soc_defs.h:628
GPP_F6
#define GPP_F6
Definition:
gpio_soc_defs.h:579
GPP_F20
#define GPP_F20
Definition:
gpio_soc_defs.h:593
GPP_F23
#define GPP_F23
Definition:
gpio_soc_defs.h:596
GPP_C5
#define GPP_C5
Definition:
gpio_soc_defs.h:542
GPP_A14
#define GPP_A14
Definition:
gpio_soc_defs.h:133
GPP_H17
#define GPP_H17
Definition:
gpio_soc_defs.h:233
GPP_D7
#define GPP_D7
Definition:
gpio_soc_defs.h:259
GPP_E6
#define GPP_E6
Definition:
gpio_soc_defs.h:634
GPP_D2
#define GPP_D2
Definition:
gpio_soc_defs.h:254
GPP_C9
#define GPP_C9
Definition:
gpio_soc_defs.h:546
GPP_H2
#define GPP_H2
Definition:
gpio_soc_defs.h:218
GPP_C22
#define GPP_C22
Definition:
gpio_soc_defs.h:559
GPD0
#define GPD0
Definition:
gpio_soc_defs.h:380
GPP_F5
#define GPP_F5
Definition:
gpio_soc_defs.h:578
GPP_C23
#define GPP_C23
Definition:
gpio_soc_defs.h:560
GPP_C8
#define GPP_C8
Definition:
gpio_soc_defs.h:545
GPP_C11
#define GPP_C11
Definition:
gpio_soc_defs.h:548
GPP_B22
#define GPP_B22
Definition:
gpio_soc_defs.h:75
GPP_F9
#define GPP_F9
Definition:
gpio_soc_defs.h:582
GPP_C13
#define GPP_C13
Definition:
gpio_soc_defs.h:550
GPP_E9
#define GPP_E9
Definition:
gpio_soc_defs.h:637
GPP_C17
#define GPP_C17
Definition:
gpio_soc_defs.h:554
GPP_E8
#define GPP_E8
Definition:
gpio_soc_defs.h:636
GPP_E5
#define GPP_E5
Definition:
gpio_soc_defs.h:633
GPD7
#define GPD7
Definition:
gpio_soc_defs.h:388
GPP_B8
#define GPP_B8
Definition:
gpio_soc_defs.h:61
GPP_C20
#define GPP_C20
Definition:
gpio_soc_defs.h:557
GPP_A16
#define GPP_A16
Definition:
gpio_soc_defs.h:135
GPP_F1
#define GPP_F1
Definition:
gpio_soc_defs.h:574
GPP_F17
#define GPP_F17
Definition:
gpio_soc_defs.h:590
GPP_F15
#define GPP_F15
Definition:
gpio_soc_defs.h:588
GPP_C10
#define GPP_C10
Definition:
gpio_soc_defs.h:547
GPP_C6
#define GPP_C6
Definition:
gpio_soc_defs.h:543
GPP_F10
#define GPP_F10
Definition:
gpio_soc_defs.h:583
GPP_C16
#define GPP_C16
Definition:
gpio_soc_defs.h:553
GPD1
#define GPD1
Definition:
gpio_soc_defs.h:382
GPP_F13
#define GPP_F13
Definition:
gpio_soc_defs.h:586
GPP_D18
#define GPP_D18
Definition:
gpio_soc_defs.h:270
GPP_E2
#define GPP_E2
Definition:
gpio_soc_defs.h:630
GPP_H0
#define GPP_H0
Definition:
gpio_soc_defs.h:215
GPP_C21
#define GPP_C21
Definition:
gpio_soc_defs.h:558
GPP_F14
#define GPP_F14
Definition:
gpio_soc_defs.h:587
GPP_H3
#define GPP_H3
Definition:
gpio_soc_defs.h:219
GPP_F4
#define GPP_F4
Definition:
gpio_soc_defs.h:577
GPP_B14
#define GPP_B14
Definition:
gpio_soc_defs.h:67
GPP_B18
#define GPP_B18
Definition:
gpio_soc_defs.h:71
GPP_C14
#define GPP_C14
Definition:
gpio_soc_defs.h:551
GPP_E10
#define GPP_E10
Definition:
gpio_soc_defs.h:638
GPP_F8
#define GPP_F8
Definition:
gpio_soc_defs.h:581
GPP_D19
#define GPP_D19
Definition:
gpio_soc_defs.h:271
GPP_F2
#define GPP_F2
Definition:
gpio_soc_defs.h:575
GPP_E11
#define GPP_E11
Definition:
gpio_soc_defs.h:639
GPP_F18
#define GPP_F18
Definition:
gpio_soc_defs.h:591
GPP_F22
#define GPP_F22
Definition:
gpio_soc_defs.h:595
GPP_F3
#define GPP_F3
Definition:
gpio_soc_defs.h:576
GPP_H10
#define GPP_H10
Definition:
gpio_soc_defs.h:226
GPP_E12
#define GPP_E12
Definition:
gpio_soc_defs.h:640
GPP_E4
#define GPP_E4
Definition:
gpio_soc_defs.h:632
GPP_E1
#define GPP_E1
Definition:
gpio_soc_defs.h:629
GPP_F19
#define GPP_F19
Definition:
gpio_soc_defs.h:592
GPP_C7
#define GPP_C7
Definition:
gpio_soc_defs.h:544
GPP_D3
#define GPP_D3
Definition:
gpio_soc_defs.h:255
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
I2S1_SFRM
#define I2S1_SFRM
Definition:
gpio_soc_defs.h:327
I2S1_TXD
#define I2S1_TXD
Definition:
gpio_soc_defs.h:328
GPP_G1
#define GPP_G1
Definition:
gpio_soc_defs.h:89
GPP_D22
#define GPP_D22
Definition:
gpio_soc_defs.h:132
GPP_G2
#define GPP_G2
Definition:
gpio_soc_defs.h:90
GPP_D21
#define GPP_D21
Definition:
gpio_soc_defs.h:131
GPP_D20
#define GPP_D20
Definition:
gpio_soc_defs.h:130
GPP_G3
#define GPP_G3
Definition:
gpio_soc_defs.h:91
GPP_K4
#define GPP_K4
Definition:
gpio_soc_defs_cnp_h.h:209
GPP_I5
#define GPP_I5
Definition:
gpio_soc_defs_cnp_h.h:340
GPP_J7
#define GPP_J7
Definition:
gpio_soc_defs_cnp_h.h:362
GPP_J4
#define GPP_J4
Definition:
gpio_soc_defs_cnp_h.h:359
GPP_K2
#define GPP_K2
Definition:
gpio_soc_defs_cnp_h.h:207
GPP_K9
#define GPP_K9
Definition:
gpio_soc_defs_cnp_h.h:214
GPP_J5
#define GPP_J5
Definition:
gpio_soc_defs_cnp_h.h:360
GPP_I10
#define GPP_I10
Definition:
gpio_soc_defs_cnp_h.h:345
GPP_J8
#define GPP_J8
Definition:
gpio_soc_defs_cnp_h.h:363
GPP_J2
#define GPP_J2
Definition:
gpio_soc_defs_cnp_h.h:357
GPP_J9
#define GPP_J9
Definition:
gpio_soc_defs_cnp_h.h:364
GPP_I8
#define GPP_I8
Definition:
gpio_soc_defs_cnp_h.h:343
GPP_J6
#define GPP_J6
Definition:
gpio_soc_defs_cnp_h.h:361
GPP_I7
#define GPP_I7
Definition:
gpio_soc_defs_cnp_h.h:342
GPP_I3
#define GPP_I3
Definition:
gpio_soc_defs_cnp_h.h:338
GPP_I6
#define GPP_I6
Definition:
gpio_soc_defs_cnp_h.h:341
GPP_J10
#define GPP_J10
Definition:
gpio_soc_defs_cnp_h.h:365
GPP_I9
#define GPP_I9
Definition:
gpio_soc_defs_cnp_h.h:344
GPP_K11
#define GPP_K11
Definition:
gpio_soc_defs_cnp_h.h:216
GPP_K21
#define GPP_K21
Definition:
gpio_soc_defs_cnp_h.h:226
GPP_K20
#define GPP_K20
Definition:
gpio_soc_defs_cnp_h.h:225
GPP_K1
#define GPP_K1
Definition:
gpio_soc_defs_cnp_h.h:206
GPP_I2
#define GPP_I2
Definition:
gpio_soc_defs_cnp_h.h:337
GPP_J11
#define GPP_J11
Definition:
gpio_soc_defs_cnp_h.h:366
GPP_J3
#define GPP_J3
Definition:
gpio_soc_defs_cnp_h.h:358
GPP_I0
#define GPP_I0
Definition:
gpio_soc_defs_cnp_h.h:335
GPP_K10
#define GPP_K10
Definition:
gpio_soc_defs_cnp_h.h:215
GPP_K5
#define GPP_K5
Definition:
gpio_soc_defs_cnp_h.h:210
GPP_K0
#define GPP_K0
Definition:
gpio_soc_defs_cnp_h.h:205
GPP_I4
#define GPP_I4
Definition:
gpio_soc_defs_cnp_h.h:339
GPP_K3
#define GPP_K3
Definition:
gpio_soc_defs_cnp_h.h:208
GPP_I1
#define GPP_I1
Definition:
gpio_soc_defs_cnp_h.h:336
GPP_K8
#define GPP_K8
Definition:
gpio_soc_defs_cnp_h.h:213
variant_configure_gpios
void variant_configure_gpios(void)
Definition:
gpio.c:238
gpio_table
static const struct pad_config gpio_table[]
Definition:
gpio.c:6
NONE
@ NONE
Definition:
qup_se_handlers_common.h:196
gpio_configure_pads
void gpio_configure_pads(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
program a particular set of GPIO
Definition:
gpio.c:307
PAD_NC
#define PAD_NC(pin)
Definition:
gpio_defs.h:263
PAD_CFG_GPI
#define PAD_CFG_GPI(pad, pull, rst)
Definition:
gpio_defs.h:284
PAD_CFG_NF
#define PAD_CFG_NF(pad, pull, rst, func)
Definition:
gpio_defs.h:197
PAD_CFG_GPI_APIC
#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv)
Definition:
gpio_defs.h:376
PAD_CFG_GPO
#define PAD_CFG_GPO(pad, val, rst)
Definition:
gpio_defs.h:247
pad_config
Definition:
gpio.h:75
src
mainboard
siemens
chili
variants
chili
gpio.c
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