coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_init.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
stdint.h
>
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#include <
bootblock_common.h
>
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#include <
device/pci_ops.h
>
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#include <
device/pnp_ops.h
>
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#include <
northbridge/intel/sandybridge/raminit_native.h
>
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#include <
option.h
>
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#include <
southbridge/intel/bd82x6x/pch.h
>
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#include <
superio/nuvoton/common/nuvoton.h
>
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#include <
superio/nuvoton/nct6776/nct6776.h
>
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#define GLOBAL_DEV PNP_DEV(0x2e, 0)
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#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
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#define GPIO6789_DEV PNP_DEV(0x2e, NCT6776_GPIO6789_V)
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/* As defined in cmos.layout */
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enum
cpu_fan_tach_src
{
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CPU_FAN_HEADER_NONE
,
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CPU_FAN_HEADER_1
,
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CPU_FAN_HEADER_2
,
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CPU_FAN_HEADER_BOTH
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};
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const
struct
southbridge_usb_port
mainboard_usb_ports
[] = {
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{ 1, 0, 0 },
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{ 1, 0, 0 },
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{ 1, 1, 1 },
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{ 1, 1, 1 },
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{ 1, 1, 2 },
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{ 1, 1, 2 },
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{ 1, 0, 3 },
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{ 1, 0, 3 },
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{ 1, 0, 4 },
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{ 1, 0, 4 },
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{ 1, 0, 6 },
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{ 1, 1, 5 },
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{ 1, 1, 5 },
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{ 1, 0, 6 },
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};
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/*
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* The tachometer signal that goes to CPUFANIN of the Super I/O is set via
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* GPIOs.
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*
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* When GP77 (register E1h[7]) is '0', CPU_FAN1 is connected.
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* When GP76 (register E1h[6]) is '0', CPU_FAN2 is connected.
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* When both are '0' and both fans are connected, wrong readings will
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* be reported.
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*/
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static
u8
get_cpufanin_gpio_config
(
void
)
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{
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switch
(
get_uint_option
(
"cpu_fan_tach_src"
,
CPU_FAN_HEADER_1
)) {
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case
CPU_FAN_HEADER_NONE
:
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return
0xff;
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case
CPU_FAN_HEADER_1
:
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default
:
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return
0x7f;
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case
CPU_FAN_HEADER_2
:
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return
0xbf;
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case
CPU_FAN_HEADER_BOTH
:
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return
0x3f;
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}
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};
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void
bootblock_mainboard_early_init
(
void
)
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{
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nuvoton_pnp_enter_conf_state
(
GLOBAL_DEV
);
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/* Configure Super I/O pins */
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pnp_write_config
(
GLOBAL_DEV
, 0x1b, 0x68);
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pnp_write_config
(
GLOBAL_DEV
, 0x1c, 0x80);
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pnp_write_config
(
GLOBAL_DEV
, 0x24, 0x5c);
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pnp_write_config
(
GLOBAL_DEV
, 0x27, 0xc0);
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pnp_write_config
(
GLOBAL_DEV
, 0x2a, 0x62);
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pnp_write_config
(
GLOBAL_DEV
, 0x2b, 0x08);
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pnp_write_config
(
GLOBAL_DEV
, 0x2c, 0x80);
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/* GP77 and GP76 are outputs. They set the tachometer input on CPUFANIN. */
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pnp_set_logical_device
(
GPIO6789_DEV
);
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pnp_write_config
(
GPIO6789_DEV
, 0xe0, 0x3f);
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pnp_write_config
(
GPIO6789_DEV
, 0xe1,
get_cpufanin_gpio_config
());
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nuvoton_pnp_exit_conf_state
(
GLOBAL_DEV
);
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/* Enable UART */
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nuvoton_enable_serial
(
SERIAL_DEV
, CONFIG_TTYS0_BASE);
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}
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void
mainboard_get_spd
(
spd_raw_data
*spd,
bool
id_only)
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{
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read_spd
(&spd[0], 0x50, id_only);
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read_spd
(&spd[1], 0x51, id_only);
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read_spd
(&spd[2], 0x52, id_only);
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read_spd
(&spd[3], 0x53, id_only);
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}
bootblock_common.h
spd_raw_data
u8 spd_raw_data[256]
Definition:
ddr3.h:156
pci_ops.h
bootblock_mainboard_early_init
void bootblock_mainboard_early_init(void)
Definition:
early_init.c:11
mainboard_get_spd
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
Definition:
early_init.c:25
mainboard_usb_ports
const struct southbridge_usb_port mainboard_usb_ports[]
Definition:
early_init.c:8
get_cpufanin_gpio_config
static u8 get_cpufanin_gpio_config(void)
Definition:
early_init.c:52
GPIO6789_DEV
#define GPIO6789_DEV
Definition:
early_init.c:16
cpu_fan_tach_src
cpu_fan_tach_src
Definition:
early_init.c:19
CPU_FAN_HEADER_NONE
@ CPU_FAN_HEADER_NONE
Definition:
early_init.c:20
CPU_FAN_HEADER_1
@ CPU_FAN_HEADER_1
Definition:
early_init.c:21
CPU_FAN_HEADER_BOTH
@ CPU_FAN_HEADER_BOTH
Definition:
early_init.c:23
CPU_FAN_HEADER_2
@ CPU_FAN_HEADER_2
Definition:
early_init.c:22
SERIAL_DEV
#define SERIAL_DEV
Definition:
early_init.c:15
GLOBAL_DEV
#define GLOBAL_DEV
Definition:
early_init.c:14
nct6776.h
read_spd
void read_spd(spd_raw_data *spd, u8 addr, bool id_only)
Definition:
raminit.c:138
nuvoton_pnp_enter_conf_state
void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev)
Definition:
early_serial.c:33
nuvoton_enable_serial
void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase)
Definition:
early_serial.c:48
nuvoton_pnp_exit_conf_state
void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev)
Definition:
early_serial.c:41
nuvoton.h
get_uint_option
unsigned int get_uint_option(const char *name, const unsigned int fallback)
Definition:
option.c:116
option.h
pnp_set_logical_device
void pnp_set_logical_device(struct device *dev)
Definition:
pnp_device.c:59
pnp_write_config
void pnp_write_config(struct device *dev, u8 reg, u8 value)
Definition:
pnp_device.c:38
pnp_ops.h
raminit_native.h
pch.h
stdint.h
u8
uint8_t u8
Definition:
stdint.h:45
southbridge_usb_port
Definition:
pch.h:56
src
mainboard
asrock
h77pro4-m
early_init.c
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