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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <arch/bootblock.h>
#include <arch/hpet.h>
#include <device/pci_ops.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h>
#include <soc/rcba.h>
#include <soc/spi.h>
#include <soc/pm.h>
#include <soc/romstage.h>
#include <southbridge/intel/common/early_spi.h>
Go to the source code of this file.
Functions | |
static void | map_rcba (void) |
static void | enable_port80_on_lpc (void) |
static void | set_spi_speed (void) |
static void | pch_enable_bars (void) |
static void | pch_early_lpc (void) |
void | uart_bootblock_init (void) |
void | bootblock_early_southbridge_init (void) |
Definition at line 112 of file bootblock.c.
References CONFIG, enable_port80_on_lpc(), enable_spi_prefetching_and_caching(), map_rcba(), pch_early_lpc(), set_spi_speed(), and uart_bootblock_init().
Definition at line 20 of file bootblock.c.
Referenced by bootblock_early_southbridge_init().
Definition at line 15 of file bootblock.c.
References PCH_DEV_LPC, pci_write_config32(), and RCBA.
Referenced by bootblock_early_southbridge_init().
Definition at line 64 of file bootblock.c.
References ACPI_BASE_ADDRESS, CNF1_LPC_EN, CNF2_LPC_EN, COMA_LPC_EN, FD, GAMEL_LPC_EN, GCS, HPET_BASE_ADDRESS, HPTC, inb(), KBC_LPC_EN, LPC_EN, LPC_IO_DEC, MC_LPC_EN, OIC, outb(), PCH_DEV_LPC, PCH_DISABLE_ALWAYS, pch_enable_bars(), pci_write_config16(), RC, RCBA16, RCBA32, RCBA32_AND_OR, RCBA32_OR, setbits32, TCO1_CNT, TCO_TMR_HLT, and void().
Referenced by bootblock_early_southbridge_init().
Definition at line 49 of file bootblock.c.
References ACPI_BASE_ADDRESS, ACPI_CNTL, ACPI_EN, GPIO_BASE, GPIO_BASE_ADDRESS, GPIO_CNTL, GPIO_EN, PCH_DEV_LPC, pci_write_config32(), pci_write_config8(), PMBASE, and RCBA.
Referenced by pch_early_lpc().
Definition at line 29 of file bootblock.c.
References SPIBAR32, SPIBAR8, SPIBAR_FDOC, SPIBAR_FDOD, and SPIBAR_SSFC.
Referenced by bootblock_early_southbridge_init().
Definition at line 97 of file uart.c.
References PCI_BASE_ADDRESS_0, PCI_COMMAND, PCI_DEV_INVALID, pci_s_write_config16(), pci_s_write_config32(), uart_console_get_pci_bdf(), uart_lpss_init(), and UART_PCI_ENABLE.
Referenced by bootblock_early_southbridge_init(), and bootblock_soc_early_init().