coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
fsp_params.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <fsp/api.h>
7 #include <fsp/util.h>
8 #include <option.h>
9 #include <intelblocks/lpss.h>
10 #include <intelblocks/xdci.h>
11 #include <soc/intel/common/vbt.h>
12 #include <soc/pci_devs.h>
13 #include <soc/ramstage.h>
14 #include <soc/soc_chip.h>
15 #include <string.h>
16 #include <types.h>
17 #include <fsp/ppi/mp_service_ppi.h>
18 
20 {
21  const struct soc_intel_icelake_config *config;
23 
24  for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
25  params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
26 
27  for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
28  params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i];
29  params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i];
30  params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i];
31  }
32 
33  for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++)
34  params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
35 }
36 
37 /* UPD parameters to be initialized before SiliconInit */
39 {
40  int i;
41  FSP_S_CONFIG *params = &supd->FspsConfig;
42 
45 
46  /* Parse device tree and enable/disable devices */
48 
49  /* Load VBT before devicetree-specific config. */
50  params->GraphicsConfigPtr = (uintptr_t)vbt_get();
51 
52  /* Use coreboot MP PPI services if Kconfig is enabled */
53  if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
55 
57 
58  params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
59 
60  params->PavpEnable = CONFIG(PAVP);
61 
62  /* Unlock upper 8 bytes of RTC RAM */
63  params->PchLockDownRtcMemoryLock = 0;
64 
65  params->CnviBtAudioOffload = config->CnviBtAudioOffload;
66  /* SATA */
67  params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
68  if (params->SataEnable) {
69  params->SataMode = config->SataMode;
70  params->SataSalpSupport = config->SataSalpSupport;
71  memcpy(params->SataPortsEnable, config->SataPortsEnable,
72  sizeof(params->SataPortsEnable));
73  memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
74  sizeof(params->SataPortsDevSlp));
75  }
76 
77  /* Lan */
78  params->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE);
79 
80  /* Audio */
81  params->PchHdaDspEnable = config->PchHdaDspEnable;
82  params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;
83  params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0;
84  params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;
85  params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0;
86  params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1;
87  params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2;
88  params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1;
89  params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2;
90  params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
91  params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
92 
93  /* disable Legacy PME */
94  memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
95 
96  /* Legacy 8254 timer support */
97  bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
98  params->Enable8254ClockGating = !use_8254;
99  params->Enable8254ClockGatingOnS3 = !use_8254;
100 
101  /*
102  * Legacy PM ACPI Timer (and TCO Timer)
103  * This *must* be 1 in any case to keep FSP from
104  * 1) enabling PM ACPI Timer emulation in uCode.
105  * 2) disabling the PM ACPI Timer.
106  * We handle both by ourself!
107  */
108  params->EnableTcoTimer = 1;
109 
110  /* S0ix */
111  params->PchPmSlpS0Enable = config->s0ix_enable;
112 
113  /* USB */
114  for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
115  params->PortUsb20Enable[i] =
116  config->usb2_ports[i].enable;
117  params->Usb2PhyPetxiset[i] =
118  config->usb2_ports[i].pre_emp_bias;
119  params->Usb2PhyTxiset[i] =
120  config->usb2_ports[i].tx_bias;
121  params->Usb2PhyPredeemp[i] =
122  config->usb2_ports[i].tx_emp_enable;
123  params->Usb2PhyPehalfbit[i] =
124  config->usb2_ports[i].pre_emp_bit;
125 
126  if (config->usb2_ports[i].enable)
127  params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
128  else
129  params->Usb2OverCurrentPin[i] = 0xff;
130  }
131 
132  for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
133  params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
134  if (config->usb3_ports[i].enable) {
135  params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
136  } else {
137  params->Usb3OverCurrentPin[i] = 0xff;
138  }
139  if (config->usb3_ports[i].tx_de_emp) {
140  params->Usb3HsioTxDeEmphEnable[i] = 1;
141  params->Usb3HsioTxDeEmph[i] =
142  config->usb3_ports[i].tx_de_emp;
143  }
144  if (config->usb3_ports[i].tx_downscale_amp) {
145  params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
146  params->Usb3HsioTxDownscaleAmp[i] =
147  config->usb3_ports[i].tx_downscale_amp;
148  }
149  }
150 
151  params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG);
152 
153  /* PCI Express */
154  for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
155  if (config->PcieClkSrcUsage[i] == 0)
156  config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
157  }
158  memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
159  sizeof(config->PcieClkSrcUsage));
160  memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
161  sizeof(config->PcieClkSrcClkReq));
162 
163  /* eMMC */
164  params->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC);
165  if (params->ScsEmmcEnabled) {
166  params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
167  params->EmmcUseCustomDlls = config->EmmcUseCustomDlls;
168  if (config->EmmcUseCustomDlls == 1) {
169  params->EmmcTxCmdDelayRegValue =
170  config->EmmcTxCmdDelayRegValue;
171  params->EmmcTxDataDelay1RegValue =
172  config->EmmcTxDataDelay1RegValue;
173  params->EmmcTxDataDelay2RegValue =
174  config->EmmcTxDataDelay2RegValue;
175  params->EmmcRxCmdDataDelay1RegValue =
176  config->EmmcRxCmdDataDelay1RegValue;
177  params->EmmcRxCmdDataDelay2RegValue =
178  config->EmmcRxCmdDataDelay2RegValue;
179  params->EmmcRxStrobeDelayRegValue =
180  config->EmmcRxStrobeDelayRegValue;
181  }
182  }
183 
184  /* SD */
185  params->ScsSdCardEnabled = is_devfn_enabled(PCH_DEVFN_SDCARD);
186  params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh;
187 
188  params->Heci3Enabled = config->Heci3Enabled;
189  params->Device4Enable = config->Device4Enable;
190 }
191 
192 /* Mainboard GPIO Configuration */
194 {
195  printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
196 }
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
Definition: fsp_params.c:879
__weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg)
Definition: fsp_params.c:915
void * memcpy(void *dest, const void *src, size_t n)
Definition: memcpy.c:7
void * memset(void *dstpp, int c, size_t len)
Definition: memset.c:12
static struct sdram_info params
Definition: sdram_configs.c:83
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define printk(level,...)
Definition: stdlib.h:16
@ PAVP
Definition: cse_layout.h:26
bool is_devfn_enabled(unsigned int devfn)
Definition: device_const.c:382
@ CONFIG
Definition: dsi_common.h:201
#define FSP_S_CONFIG
Definition: fsp_upd.h:9
static void parse_devicetree(FSP_S_CONFIG *params)
Definition: fsp_params.c:19
#define config_of_soc()
Definition: device.h:394
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
enum board_config config
Definition: memory.c:448
void * mp_fill_ppi_services_data(void)
Definition: mp_service1.c:73
unsigned int get_uint_option(const char *name, const unsigned int fallback)
Definition: option.c:116
const struct smm_save_state_ops *legacy_ops __weak
Definition: save_state.c:8
void * vbt_get(void)
Definition: graphics.c:131
#define PCH_DEVFN_USBOTG
Definition: pci_devs.h:125
#define PCH_DEVFN_SATA
Definition: pci_devs.h:158
#define PCH_DEVFN_GBE
Definition: pci_devs.h:221
#define SA_DEVFN_IGD
Definition: pci_devs.h:32
#define PCH_DEVFN_SDCARD
Definition: pci_devs.h:144
#define PCH_DEVFN_EMMC
Definition: pci_devs.h:148
#define PCIE_CLK_NOTUSED
Definition: pch.h:6
unsigned long uintptr_t
Definition: stdint.h:21
bool xdci_can_enable(unsigned int xdci_devfn)
Definition: xdci.c:11