12 #include <soc/pci_devs.h>
13 #include <soc/ramstage.h>
14 #include <soc/soc_chip.h>
24 for (
int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
27 for (
int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
28 params->SerialIoSpiMode[i] =
config->SerialIoGSpiMode[i];
29 params->SerialIoSpiCsMode[i] =
config->SerialIoGSpiCsMode[i];
30 params->SerialIoSpiCsState[i] =
config->SerialIoGSpiCsState[i];
33 for (
int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++)
34 params->SerialIoUartMode[i] =
config->SerialIoUartMode[i];
53 if (
CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
63 params->PchLockDownRtcMemoryLock = 0;
72 sizeof(
params->SataPortsEnable));
74 sizeof(
params->SataPortsDevSlp));
83 params->PchHdaAudioLinkDmic0 =
config->PchHdaAudioLinkDmic0;
84 params->PchHdaAudioLinkDmic1 =
config->PchHdaAudioLinkDmic1;
85 params->PchHdaAudioLinkSsp0 =
config->PchHdaAudioLinkSsp0;
86 params->PchHdaAudioLinkSsp1 =
config->PchHdaAudioLinkSsp1;
87 params->PchHdaAudioLinkSsp2 =
config->PchHdaAudioLinkSsp2;
88 params->PchHdaAudioLinkSndw1 =
config->PchHdaAudioLinkSndw1;
89 params->PchHdaAudioLinkSndw2 =
config->PchHdaAudioLinkSndw2;
90 params->PchHdaAudioLinkSndw3 =
config->PchHdaAudioLinkSndw3;
91 params->PchHdaAudioLinkSndw4 =
config->PchHdaAudioLinkSndw4;
98 params->Enable8254ClockGating = !use_8254;
99 params->Enable8254ClockGatingOnS3 = !use_8254;
108 params->EnableTcoTimer = 1;
115 params->PortUsb20Enable[i] =
116 config->usb2_ports[i].enable;
117 params->Usb2PhyPetxiset[i] =
118 config->usb2_ports[i].pre_emp_bias;
119 params->Usb2PhyTxiset[i] =
120 config->usb2_ports[i].tx_bias;
121 params->Usb2PhyPredeemp[i] =
122 config->usb2_ports[i].tx_emp_enable;
123 params->Usb2PhyPehalfbit[i] =
124 config->usb2_ports[i].pre_emp_bit;
126 if (
config->usb2_ports[i].enable)
127 params->Usb2OverCurrentPin[i] =
config->usb2_ports[i].ocpin;
129 params->Usb2OverCurrentPin[i] = 0xff;
133 params->PortUsb30Enable[i] =
config->usb3_ports[i].enable;
134 if (
config->usb3_ports[i].enable) {
135 params->Usb3OverCurrentPin[i] =
config->usb3_ports[i].ocpin;
137 params->Usb3OverCurrentPin[i] = 0xff;
139 if (
config->usb3_ports[i].tx_de_emp) {
140 params->Usb3HsioTxDeEmphEnable[i] = 1;
141 params->Usb3HsioTxDeEmph[i] =
142 config->usb3_ports[i].tx_de_emp;
144 if (
config->usb3_ports[i].tx_downscale_amp) {
145 params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
146 params->Usb3HsioTxDownscaleAmp[i] =
147 config->usb3_ports[i].tx_downscale_amp;
155 if (
config->PcieClkSrcUsage[i] == 0)
159 sizeof(
config->PcieClkSrcUsage));
161 sizeof(
config->PcieClkSrcClkReq));
165 if (
params->ScsEmmcEnabled) {
166 params->ScsEmmcHs400Enabled =
config->ScsEmmcHs400Enabled;
168 if (
config->EmmcUseCustomDlls == 1) {
169 params->EmmcTxCmdDelayRegValue =
170 config->EmmcTxCmdDelayRegValue;
171 params->EmmcTxDataDelay1RegValue =
172 config->EmmcTxDataDelay1RegValue;
173 params->EmmcTxDataDelay2RegValue =
174 config->EmmcTxDataDelay2RegValue;
175 params->EmmcRxCmdDataDelay1RegValue =
176 config->EmmcRxCmdDataDelay1RegValue;
177 params->EmmcRxCmdDataDelay2RegValue =
178 config->EmmcRxCmdDataDelay2RegValue;
179 params->EmmcRxStrobeDelayRegValue =
180 config->EmmcRxStrobeDelayRegValue;
186 params->SdCardPowerEnableActiveHigh =
config->SdCardPowerEnableActiveHigh;
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
__weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg)
void * memcpy(void *dest, const void *src, size_t n)
void * memset(void *dstpp, int c, size_t len)
static struct sdram_info params
#define printk(level,...)
bool is_devfn_enabled(unsigned int devfn)
static void parse_devicetree(FSP_S_CONFIG *params)
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
void * mp_fill_ppi_services_data(void)
unsigned int get_uint_option(const char *name, const unsigned int fallback)
const struct smm_save_state_ops *legacy_ops __weak
bool xdci_can_enable(unsigned int xdci_devfn)