coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
report_platform.c File Reference
#include <arch/cpu.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/intel/cpu_ids.h>
#include <cpu/intel/microcode.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/name.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <soc/bootblock.h>
#include <soc/pch.h>
#include <soc/pci_devs.h>
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Functions

static uint8_t get_dev_revision (pci_devfn_t dev)
 
static uint16_t get_dev_id (pci_devfn_t dev)
 
static void report_cpu_info (void)
 
static void report_mch_info (void)
 
static void report_pch_info (void)
 
static void report_igd_info (void)
 
void report_platform_info (void)
 

Variables

struct {
   u32   cpuid
 
   const char *   name
 
cpu_table []
 
struct {
   u16   mchid
 
   const char *   name
 
mch_table []
 
struct {
   u16   lpcid
 
   const char *   name
 
pch_table []
 
struct {
   u16   igdid
 
   const char *   name
 
igd_table []
 

Function Documentation

◆ get_dev_id()

static uint16_t get_dev_id ( pci_devfn_t  dev)
static

Definition at line 164 of file report_platform.c.

References PCI_DEVICE_ID, and pci_read_config16().

Referenced by report_igd_info(), report_mch_info(), and report_pch_info().

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◆ get_dev_revision()

static uint8_t get_dev_revision ( pci_devfn_t  dev)
static

Definition at line 159 of file report_platform.c.

References pci_read_config8(), and PCI_REVISION_ID.

Referenced by report_igd_info(), report_mch_info(), and report_pch_info().

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◆ report_cpu_info()

static void report_cpu_info ( void  )
static

Definition at line 169 of file report_platform.c.

References ARRAY_SIZE, BIOS_DEBUG, cpu_get_cpuid(), cpu_get_feature_flags_ecx(), cpu_id, cpu_table, cpuid, CPUID_AES, CPUID_SMX, CPUID_VMX, fill_processor_name(), get_current_microcode_rev(), and printk.

Referenced by report_platform_info().

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◆ report_igd_info()

static void report_igd_info ( void  )
static

Definition at line 237 of file report_platform.c.

References ARRAY_SIZE, BIOS_DEBUG, get_dev_id(), get_dev_revision(), igd_table, igdid, printk, and SA_DEV_IGD.

Referenced by report_platform_info().

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◆ report_mch_info()

static void report_mch_info ( void  )
static

Definition at line 201 of file report_platform.c.

References ARRAY_SIZE, BIOS_DEBUG, get_dev_id(), get_dev_revision(), mch_table, mchid, printk, and SA_DEV_ROOT.

Referenced by report_platform_info().

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◆ report_pch_info()

static void report_pch_info ( void  )
static

Definition at line 220 of file report_platform.c.

References ARRAY_SIZE, BIOS_DEBUG, get_dev_id(), get_dev_revision(), lpcid, PCH_DEV_LPC, pch_table, pch_type(), and printk.

Referenced by report_platform_info().

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◆ report_platform_info()

void report_platform_info ( void  )

Definition at line 254 of file report_platform.c.

References report_cpu_info(), report_igd_info(), report_mch_info(), and report_pch_info().

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Variable Documentation

◆ 

struct { ... } cpu_table[]
Initial value:
= {
{ CPUID_CANNONLAKE_A0, "Cannonlake A0" },
{ CPUID_CANNONLAKE_B0, "Cannonlake B0" },
{ CPUID_CANNONLAKE_C0, "Cannonlake C0" },
{ CPUID_CANNONLAKE_D0, "Cannonlake D0" },
{ CPUID_KABYLAKE_Y0, "Coffeelake D0" },
{ CPUID_WHISKEYLAKE_V0, "Whiskeylake V0" },
{ CPUID_WHISKEYLAKE_W0, "Whiskeylake W0" },
{ CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" },
{ CPUID_COFFEELAKE_B0, "Coffeelake B0" },
{ CPUID_COFFEELAKE_P0, "Coffeelake P0" },
{ CPUID_COFFEELAKE_R0, "Coffeelake R0" },
{ CPUID_COMETLAKE_U_A0, "Cometlake-U A0 (6+2)" },
{ CPUID_COMETLAKE_U_K0_S0, "Cometlake-U K0/S0 (6+2)/(4+2)" },
{ CPUID_COMETLAKE_H_S_6_2_G0, "Cometlake-H/S G0 (6+2)" },
{ CPUID_COMETLAKE_H_S_6_2_G1, "Cometlake-H/S G1 (6+2)" },
{ CPUID_COMETLAKE_H_S_10_2_P0, "Cometlake-H/S P0 (10+2)" },
{ CPUID_COMETLAKE_H_S_10_2_Q0_P1, "Cometlake-H/S Q0/P1 (10+2)" },
}
#define CPUID_KABYLAKE_Y0
Definition: cpu_ids.h:20
#define CPUID_COMETLAKE_H_S_6_2_G0
Definition: cpu_ids.h:44
#define CPUID_COMETLAKE_U_K0_S0
Definition: cpu_ids.h:43
#define CPUID_CANNONLAKE_B0
Definition: cpu_ids.h:24
#define CPUID_COMETLAKE_H_S_10_2_Q0_P1
Definition: cpu_ids.h:47
#define CPUID_WHISKEYLAKE_V0
Definition: cpu_ids.h:33
#define CPUID_COMETLAKE_H_S_10_2_P0
Definition: cpu_ids.h:46
#define CPUID_COFFEELAKE_P0
Definition: cpu_ids.h:37
#define CPUID_CANNONLAKE_A0
Definition: cpu_ids.h:23
#define CPUID_CANNONLAKE_C0
Definition: cpu_ids.h:25
#define CPUID_COFFEELAKE_B0
Definition: cpu_ids.h:36
#define CPUID_CANNONLAKE_D0
Definition: cpu_ids.h:26
#define CPUID_COMETLAKE_H_S_6_2_G1
Definition: cpu_ids.h:45
#define CPUID_WHISKEYLAKE_W0
Definition: cpu_ids.h:34
#define CPUID_COFFEELAKE_U0
Definition: cpu_ids.h:35
#define CPUID_COFFEELAKE_R0
Definition: cpu_ids.h:38
#define CPUID_COMETLAKE_U_A0
Definition: cpu_ids.h:42

Referenced by report_cpu_info().

◆ cpuid

u32 cpuid

Definition at line 17 of file report_platform.c.

◆ 

struct { ... } igd_table[]

Referenced by report_igd_info().

◆ igdid

u16 igdid

Definition at line 109 of file report_platform.c.

◆ lpcid

u16 lpcid

Definition at line 78 of file report_platform.c.

◆ 

struct { ... } mch_table[]

Referenced by report_mch_info().

◆ mchid

u16 mchid

Definition at line 40 of file report_platform.c.

◆ name

const char* name

Definition at line 18 of file report_platform.c.

◆ 

struct { ... } pch_table[]
Initial value:
= {
{ PCI_DID_INTEL_CNL_BASE_U_LPC, "Cannonlake-U Base" },
{ PCI_DID_INTEL_CNL_U_PREMIUM_LPC, "Cannonlake-U Premium" },
{ PCI_DID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" },
{ PCI_DID_INTEL_CNP_H_LPC_H310, "Cannonlake-H H310" },
{ PCI_DID_INTEL_CNP_H_LPC_H370, "Cannonlake-H H370" },
{ PCI_DID_INTEL_CNP_H_LPC_Z390, "Cannonlake-H Z390" },
{ PCI_DID_INTEL_CNP_H_LPC_Q370, "Cannonlake-H Q370" },
{ PCI_DID_INTEL_CNP_H_LPC_B360, "Cannonlake-H B360" },
{ PCI_DID_INTEL_CNP_H_LPC_C246, "Cannonlake-H C246" },
{ PCI_DID_INTEL_CNP_H_LPC_C242, "Cannonlake-H C242" },
{ PCI_DID_INTEL_CNP_H_LPC_QM370, "Cannonlake-H QM370" },
{ PCI_DID_INTEL_CNP_H_LPC_HM370, "Cannonlake-H HM370" },
{ PCI_DID_INTEL_CNP_H_LPC_CM246, "Cannonlake-H CM246" },
{ PCI_DID_INTEL_CMP_SUPER_U_LPC, "Cometlake-U Super" },
{ PCI_DID_INTEL_CMP_PREMIUM_Y_LPC, "Cometlake-Y Premium" },
{ PCI_DID_INTEL_CMP_PREMIUM_U_LPC, "Cometlake-U Premium" },
{ PCI_DID_INTEL_CMP_BASE_U_LPC, "Cometlake-U Base" },
{ PCI_DID_INTEL_CMP_SUPER_Y_LPC, "Cometlake-Y Super" },
{ PCI_DID_INTEL_CMP_H_LPC_HM470, "Cometlake-H HM470" },
{ PCI_DID_INTEL_CMP_H_LPC_WM490, "Cometlake-H WM490" },
{ PCI_DID_INTEL_CMP_H_LPC_QM480, "Cometlake-H QM480" },
{ PCI_DID_INTEL_CMP_H_LPC_W480, "Cometlake-H W480" },
{ PCI_DID_INTEL_CMP_H_LPC_H470, "Cometlake-H H470" },
{ PCI_DID_INTEL_CMP_H_LPC_Z490, "Cometlake-H Z490" },
{ PCI_DID_INTEL_CMP_H_LPC_Q470, "Cometlake-H Q470" },
}
#define PCI_DID_INTEL_CNP_H_LPC_H370
Definition: pci_ids.h:2900
#define PCI_DID_INTEL_CNL_U_PREMIUM_LPC
Definition: pci_ids.h:2897
#define PCI_DID_INTEL_CMP_SUPER_Y_LPC
Definition: pci_ids.h:2920
#define PCI_DID_INTEL_CNL_Y_PREMIUM_LPC
Definition: pci_ids.h:2898
#define PCI_DID_INTEL_CMP_H_LPC_Z490
Definition: pci_ids.h:2926
#define PCI_DID_INTEL_CMP_H_LPC_HM470
Definition: pci_ids.h:2921
#define PCI_DID_INTEL_CMP_SUPER_U_LPC
Definition: pci_ids.h:2916
#define PCI_DID_INTEL_CNP_H_LPC_HM370
Definition: pci_ids.h:2907
#define PCI_DID_INTEL_CMP_H_LPC_W480
Definition: pci_ids.h:2924
#define PCI_DID_INTEL_CMP_PREMIUM_Y_LPC
Definition: pci_ids.h:2917
#define PCI_DID_INTEL_CNP_H_LPC_C246
Definition: pci_ids.h:2904
#define PCI_DID_INTEL_CMP_H_LPC_Q470
Definition: pci_ids.h:2927
#define PCI_DID_INTEL_CMP_H_LPC_H470
Definition: pci_ids.h:2925
#define PCI_DID_INTEL_CMP_H_LPC_WM490
Definition: pci_ids.h:2922
#define PCI_DID_INTEL_CMP_PREMIUM_U_LPC
Definition: pci_ids.h:2918
#define PCI_DID_INTEL_CNP_H_LPC_B360
Definition: pci_ids.h:2903
#define PCI_DID_INTEL_CNP_H_LPC_CM246
Definition: pci_ids.h:2908
#define PCI_DID_INTEL_CNP_H_LPC_Q370
Definition: pci_ids.h:2902
#define PCI_DID_INTEL_CNP_H_LPC_Z390
Definition: pci_ids.h:2901
#define PCI_DID_INTEL_CNP_H_LPC_H310
Definition: pci_ids.h:2899
#define PCI_DID_INTEL_CMP_BASE_U_LPC
Definition: pci_ids.h:2919
#define PCI_DID_INTEL_CNL_BASE_U_LPC
Definition: pci_ids.h:2896
#define PCI_DID_INTEL_CNP_H_LPC_C242
Definition: pci_ids.h:2905
#define PCI_DID_INTEL_CMP_H_LPC_QM480
Definition: pci_ids.h:2923
#define PCI_DID_INTEL_CNP_H_LPC_QM370
Definition: pci_ids.h:2906

Referenced by report_pch_info().