12 #include <soc/bootblock.h>
14 #include <soc/pci_devs.h>
174 static const char *
const mode[] = {
"NOT ",
""};
193 aes = (cpu_feature_flag &
CPUID_AES) ? 1 : 0;
194 txt = (cpu_feature_flag &
CPUID_SMX) ? 1 : 0;
195 vt = (cpu_feature_flag &
CPUID_VMX) ? 1 : 0;
197 "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
198 mode[aes], mode[txt], mode[vt]);
207 const char *mch_type =
"Unknown";
217 mchid, mch_revision, mch_type);
242 const char *igd_type =
"Unknown";
#define printk(level,...)
uint32_t cpu_get_feature_flags_ecx(void)
uint32_t cpu_get_cpuid(void)
#define CPUID_KABYLAKE_Y0
#define CPUID_COMETLAKE_H_S_6_2_G0
#define CPUID_COMETLAKE_U_K0_S0
#define CPUID_CANNONLAKE_B0
#define CPUID_COMETLAKE_H_S_10_2_Q0_P1
#define CPUID_WHISKEYLAKE_V0
#define CPUID_COMETLAKE_H_S_10_2_P0
#define CPUID_COFFEELAKE_P0
#define CPUID_CANNONLAKE_A0
#define CPUID_CANNONLAKE_C0
#define CPUID_COFFEELAKE_B0
#define CPUID_CANNONLAKE_D0
#define CPUID_COMETLAKE_H_S_6_2_G1
#define CPUID_WHISKEYLAKE_W0
#define CPUID_COFFEELAKE_U0
#define CPUID_COFFEELAKE_R0
#define CPUID_COMETLAKE_U_A0
static __always_inline u16 pci_read_config16(const struct device *dev, u16 reg)
static __always_inline u8 pci_read_config8(const struct device *dev, u16 reg)
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
uint32_t get_current_microcode_rev(void)
void fill_processor_name(char *processor_name)
#define PCI_DID_INTEL_CML_H_4_2
#define PCI_DID_INTEL_CML_GT2_ULT_6
#define PCI_DID_INTEL_CNP_H_LPC_H370
#define PCI_DID_INTEL_CML_GT1_S_1
#define PCI_DID_INTEL_CNL_U_PREMIUM_LPC
#define PCI_DID_INTEL_CML_GT1_ULT_1
#define PCI_DID_INTEL_CFL_H_GT2
#define PCI_DID_INTEL_CMP_SUPER_Y_LPC
#define PCI_DID_INTEL_CNL_GT2_ULT_4
#define PCI_DID_INTEL_CNL_Y_PREMIUM_LPC
#define PCI_DID_INTEL_CML_GT2_ULT_4
#define PCI_DID_INTEL_CFL_ID_U
#define PCI_DID_INTEL_WHL_GT2_ULT_1
#define PCI_DID_INTEL_CNL_GT2_ULX_2
#define PCI_DID_INTEL_CML_S_P0P1_10_2
#define PCI_DID_INTEL_CMP_H_LPC_Z490
#define PCI_DID_INTEL_CML_GT2_S_1
#define PCI_DID_INTEL_CML_GT2_ULT_2
#define PCI_DID_INTEL_CFL_S_GT2_4
#define PCI_DID_INTEL_CMP_H_LPC_HM470
#define PCI_DID_INTEL_CML_GT1_ULX_1
#define PCI_DID_INTEL_CMP_SUPER_U_LPC
#define PCI_DID_INTEL_CML_GT2_ULX_1
#define PCI_DID_INTEL_CNP_H_LPC_HM370
#define PCI_DID_INTEL_CFL_ID_S_WS_4
#define PCI_DID_INTEL_CMP_H_LPC_W480
#define PCI_DID_INTEL_CNL_GT2_ULX_3
#define PCI_DID_INTEL_CMP_PREMIUM_Y_LPC
#define PCI_DID_INTEL_CFL_ID_S_S_6
#define PCI_DID_INTEL_CML_S_P0P1_8_2
#define PCI_DID_INTEL_WHL_ID_W_4
#define PCI_DID_INTEL_CML_GT2_S_2
#define PCI_DID_INTEL_CFL_S_GT2_2
#define PCI_DID_INTEL_CML_S_G0G1_2
#define PCI_DID_INTEL_CML_GT2_S_G0
#define PCI_DID_INTEL_CNP_H_LPC_C246
#define PCI_DID_INTEL_CML_GT2_ULT_1
#define PCI_DID_INTEL_CMP_H_LPC_Q470
#define PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2
#define PCI_DID_INTEL_CMP_H_LPC_H470
#define PCI_DID_INTEL_CFL_ID_S_WS_8
#define PCI_DID_INTEL_CFL_ID_S_DT_2
#define PCI_DID_INTEL_CMP_H_LPC_WM490
#define PCI_DID_INTEL_CML_GT2_H_R1
#define PCI_DID_INTEL_CFL_S_GT2_3
#define PCI_DID_INTEL_CFL_S_GT1_1
#define PCI_DID_INTEL_CNL_GT2_ULT_3
#define PCI_DID_INTEL_CNL_GT2_ULT_2
#define PCI_DID_INTEL_CML_GT1_ULT_3
#define PCI_DID_INTEL_CML_GT1_ULT_4
#define PCI_DID_INTEL_CML_GT2_H_1
#define PCI_DID_INTEL_CML_GT1_H_2
#define PCI_DID_INTEL_CFL_ID_H_8
#define PCI_DID_INTEL_CFL_ID_S
#define PCI_DID_INTEL_CNL_ID_U
#define PCI_DID_INTEL_CML_GT2_S_P0
#define PCI_DID_INTEL_CFL_ID_S_DT_4
#define PCI_DID_INTEL_CFL_ID_H_4
#define PCI_DID_INTEL_CMP_PREMIUM_U_LPC
#define PCI_DID_INTEL_CNL_GT2_ULX_4
#define PCI_DID_INTEL_CFL_ID_U_2
#define PCI_DID_INTEL_CML_ULT_6_2
#define PCI_DID_INTEL_CNP_H_LPC_B360
#define PCI_DID_INTEL_CML_S_G0G1_4
#define PCI_DID_INTEL_CFL_GT2_ULT
#define PCI_DID_INTEL_CNP_H_LPC_CM246
#define PCI_DID_INTEL_CNL_ID_Y
#define PCI_DID_INTEL_CFL_ID_S_WS_6
#define PCI_DID_INTEL_CNP_H_LPC_Q370
#define PCI_DID_INTEL_CFL_ID_S_DT_8
#define PCI_DID_INTEL_CFL_ID_H
#define PCI_DID_INTEL_WHL_GT1_ULT_1
#define PCI_DID_INTEL_CML_ULT
#define PCI_DID_INTEL_CML_GT1_ULT_2
#define PCI_DID_INTEL_CNP_H_LPC_Z390
#define PCI_DID_INTEL_CNP_H_LPC_H310
#define PCI_DID_INTEL_CMP_BASE_U_LPC
#define PCI_DID_INTEL_CML_GT2_ULT_3
#define PCI_DID_INTEL_CML_GT2_H_2
#define PCI_DID_INTEL_CFL_H_XEON_GT2
#define PCI_DID_INTEL_CNL_BASE_U_LPC
#define PCI_DID_INTEL_CNL_GT2_ULX_1
#define PCI_DID_INTEL_CML_ULX
#define PCI_DID_INTEL_CFL_S_GT1_2
#define PCI_DID_INTEL_CML_GT2_H_R0
#define PCI_DID_INTEL_CML_H_8_2
#define PCI_DID_INTEL_CFL_ID_S_S_8
#define PCI_DID_INTEL_CML_GT1_H_1
#define PCI_DID_INTEL_CML_S
#define PCI_DID_INTEL_CML_ULT_2_2
#define PCI_DID_INTEL_CFL_S_GT2_5
#define PCI_DID_INTEL_CML_GT1_S_2
#define PCI_DID_INTEL_WHL_ID_W_2
#define PCI_DID_INTEL_CFL_ID_S_S_4
#define PCI_DID_INTEL_CNP_H_LPC_C242
#define PCI_DID_INTEL_CFL_S_GT2_1
#define PCI_DID_INTEL_CMP_H_LPC_QM480
#define PCI_DID_INTEL_CNP_H_LPC_QM370
#define PCI_DID_INTEL_CML_H
#define PCI_DID_INTEL_CNL_GT2_ULT_1
#define PCI_DID_INTEL_CML_GT2_ULT_5