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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <stdint.h>
Go to the source code of this file.
Functions | |
u16 | lpc_get_pmbase (void) |
void | write_pmbase32 (const u8 addr, const u32 val) |
void | write_pmbase16 (const u8 addr, const u16 val) |
void | write_pmbase8 (const u8 addr, const u8 val) |
u32 | read_pmbase32 (const u8 addr) |
u16 | read_pmbase16 (const u8 addr) |
u8 | read_pmbase8 (const u8 addr) |
Definition at line 19 of file pmbase.c.
References PCI_DEV, pci_read_config16(), pcidev_on_root(), PMBASE, and pmbase.
Referenced by acpi_fill_fadt(), get_pmbase(), read_pmbase16(), read_pmbase32(), read_pmbase8(), smi_enabled(), write_pmbase16(), write_pmbase32(), and write_pmbase8().
Definition at line 64 of file pmbase.c.
References addr, ASSERT, inw(), lpc_get_pmbase(), and PMSIZE.
Referenced by alt_gpi_mask(), dump_pm1_status(), early_usb_init(), intel_pch_finalize_smm(), platform_is_resuming(), reset_alt_gp_smi_status(), reset_pm1_status(), southbridge_smi_gpi(), and watchdog_off().
Definition at line 57 of file pmbase.c.
References addr, ASSERT, inl(), lpc_get_pmbase(), and PMSIZE.
Referenced by acpi_get_sleep_type(), clear_power_state(), gpe0_mask(), i82801gx_power_options(), intel_txt_romstage_init(), mainboard_smi_ec(), mainboard_smi_gpi(), raminit(), reset_gpe0_status(), reset_smi_status(), reset_tco_status(), smi_enabled(), smm_southbridge_enable(), southbridge_smi_apmc(), southbridge_smi_mc(), southbridge_smi_periodic(), southbridge_smi_sleep(), and stout_ec_finalize_smm().
Definition at line 71 of file pmbase.c.
References addr, ASSERT, inb(), lpc_get_pmbase(), and PMSIZE.
Referenced by smi_set_eos(), southbridge_smi_set_eos(), and southbridge_smi_sleep().
Definition at line 43 of file pmbase.c.
References addr, ASSERT, lpc_get_pmbase(), outw(), PMSIZE, and val.
Referenced by alt_gpi_mask(), early_usb_init(), i82801gx_power_options(), i82801jx_early_init(), intel_pch_finalize_smm(), pch_generic_setup(), reset_alt_gp_smi_status(), reset_pm1_status(), smm_southbridge_enable(), southbridge_smi_gpi(), and watchdog_off().
Definition at line 36 of file pmbase.c.
References addr, ASSERT, lpc_get_pmbase(), outl(), PMSIZE, and val.
Referenced by clear_power_state(), gpe0_mask(), i82801gx_power_options(), intel_txt_romstage_init(), mainboard_smi_ec(), mainboard_smi_gpi(), raminit(), reset_gpe0_status(), reset_smi_status(), reset_tco_status(), smm_southbridge_enable(), southbridge_smi_apmc(), southbridge_smi_pm1(), southbridge_smi_sleep(), and stout_ec_finalize_smm().
Definition at line 50 of file pmbase.c.
References addr, ASSERT, lpc_get_pmbase(), outb(), PMSIZE, and val.
Referenced by smi_set_eos(), southbridge_smi_set_eos(), and southbridge_smi_sleep().