#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <device/smbus_host.h>
#include <lib.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <assert.h>
#include <spd.h>
#include <sdram_mode.h>
#include <timestamp.h>
#include "raminit.h"
#include "e7505.h"

Include dependency graph for raminit.c:

Data Structures
struct	dimm_size

Macros
#define	RAM_DEBUG_MESSAGE(x)

#define	RAM_DEBUG_HEX32(x)

#define	RAM_DEBUG_HEX8(x)

#define	E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED \| SDRAM_BURST_4)

#define	SPD_ERROR "Error reading SPD info\n"

#define	MCHDEV PCI_DEV(0, 0, 0)

#define	RASDEV PCI_DEV(0, 0, 1)

#define	AGPDEV PCI_DEV(0, 1, 0)

#define	D060DEV PCI_DEV(0, 6, 0)

#define	RCOMP_MMIO ((u8 *)0x200000)

#define	MAX_SPD_REFRESH_RATE (ARRAY_SIZE(refresh_rate_map) - 1)

#define	SLOW_DOWN_IO inb(0x80)

#define	DO_DELAY local_udelay(200)

#define	EXTRA_DELAY DO_DELAY

Enumerations
enum	mchtst_cc { MCHTST_CMD_0 , D060_ENABLE , D060_DISABLE , RCOMP_BAR_ENABLE , RCOMP_BAR_DISABLE }

enum	d060_cc { D060_CMD_0 , D060_CMD_1 }

enum	rcomp_smr_cc { RCOMP_HOLD , RCOMP_RELEASE , RCOMP_SMR_00 , RCOMP_SMR_01 }

Functions
static void	local_udelay (int i)

static void	mchtest_control (mchtst_cc cmd)
	MCHTST - 0xF4 - 0xF7 – Based on similarity to 855PM. More...

static void	d060_control (d060_cc cmd)

static void	rcomp_smr_control (rcomp_smr_cc cmd)

static void	die_on_spd_error (int spd_return_value)

static struct dimm_size	sdram_spd_get_page_size (uint16_t dimm_socket_address)
	Calculate the page size for each physical bank of the DIMM: log2(page size) = (# columns) + log2(data width) More...

static struct dimm_size	sdram_spd_get_width (uint16_t dimm_socket_address)
	Read the width in bits of each DIMM side's DRAMs via SPD (i.e. More...

static struct dimm_size	spd_get_dimm_size (unsigned int dimm_socket_address)
	Calculate the log base 2 size in bits of both DIMM sides. More...

static uint8_t	are_spd_values_equal (uint8_t spd_byte_number, uint16_t dimm0_address, uint16_t dimm1_address)
	Determine whether two DIMMs have the same value for an SPD parameter. More...

static uint8_t	spd_get_supported_dimms (const struct mem_controller *ctrl)
	Scan for compatible DIMMs. More...

static void	do_ram_command (uint8_t command, uint16_t jedec_mode_bits)
	Send the specified command to all DIMMs. More...

static void	set_ram_mode (uint16_t jedec_mode_bits)
	Set the mode register of all DIMMs. More...

static uint8_t	configure_dimm_row_boundaries (struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned int dimm_index)
	Configure the E7501's DRAM Row Boundary (DRB) registers for the memory present in the specified DIMM. More...

static void	configure_e7501_ram_addresses (const struct mem_controller *ctrl, uint8_t dimm_mask)
	Set the E7501's DRAM row boundary addresses & its Top Of Low Memory (TOLM). More...

static void	configure_e7501_dram_timing (const struct mem_controller *ctrl, uint8_t dimm_mask)
	Program the DRAM Timing register (DRT) of the E7501 (except for CAS# latency, which is assumed to have been programmed already), based on the parameters of the various installed DIMMs. More...

static void	configure_e7501_cas_latency (const struct mem_controller *ctrl, uint8_t dimm_mask)
	Determine the shortest CAS# latency that the E7501 and all DIMMs have in common, and program the E7501 to use it. More...

static void	configure_e7501_dram_controller_mode (const struct mem_controller *ctrl, uint8_t dimm_mask)
	Configure the refresh interval so that we refresh no more often than required by the "most needy" DIMM. More...

static void	configure_e7501_row_attributes (const struct mem_controller *ctrl, uint8_t dimm_mask)
	Configure the E7501's DRAM Row Attributes (DRA) registers based on DIMM parameters read via SPD. More...

static void	enable_e7501_clocks (uint8_t dimm_mask)

static void	RAM_RESET_DDR_PTR (void)
	DDR Receive FIFO RE-Sync (?) More...

static void	write_8dwords (const uint32_t src_addr, u8 dst_addr)
	Copy 64 bytes from one location to another. More...

static void	rcomp_copy_registers (void)
	Set the E7501's (undocumented) RCOMP registers. More...

static void	ram_set_rcomp_regs (void)

static void	sdram_enable (const struct mem_controller *ctrl)
	Go through the JEDEC initialization sequence for all DIMMs, then enable refresh and initialize ECC and memory to zero. More...

static void	sdram_post_ecc (const struct mem_controller *ctrl)

static void	sdram_set_spd_registers (const struct mem_controller *ctrl)
	Configure SDRAM controller parameters that depend on characteristics of the DIMMs installed in the system. More...

static void	sdram_set_registers (const struct mem_controller *ctrl)
	Do basic RAM setup that does NOT depend on serial presence detect information (i.e. More...

static int	e7505_mch_is_ready (void)

void	sdram_initialize (void)

Variables
static const uint32_t	refresh_frequency []

static const uint32_t	refresh_rate_map []

static const uint8_t	dual_channel_parameters []

static const uint32_t	slew_2x []

static const uint32_t	pull_updown_offset_table []

Macro Definition Documentation

◆ AGPDEV

#define AGPDEV PCI_DEV(0, 1, 0)

Definition at line 50 of file raminit.c.

◆ D060DEV

#define D060DEV PCI_DEV(0, 6, 0)

Definition at line 51 of file raminit.c.

◆ DO_DELAY

#define DO_DELAY local_udelay(200)

Definition at line 181 of file raminit.c.

◆ E7501_SDRAM_MODE

#define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4)

Definition at line 45 of file raminit.c.

◆ EXTRA_DELAY

#define EXTRA_DELAY DO_DELAY

Definition at line 182 of file raminit.c.

◆ MAX_SPD_REFRESH_RATE

#define MAX_SPD_REFRESH_RATE (ARRAY_SIZE(refresh_rate_map) - 1)

Definition at line 95 of file raminit.c.

◆ MCHDEV

#define MCHDEV PCI_DEV(0, 0, 0)

Definition at line 48 of file raminit.c.

◆ RAM_DEBUG_HEX32

#define RAM_DEBUG_HEX32 ( x )

Definition at line 41 of file raminit.c.

◆ RAM_DEBUG_HEX8

#define RAM_DEBUG_HEX8 ( x )

Definition at line 42 of file raminit.c.

◆ RAM_DEBUG_MESSAGE

#define RAM_DEBUG_MESSAGE ( x )

Definition at line 40 of file raminit.c.

◆ RASDEV

#define RASDEV PCI_DEV(0, 0, 1)

Definition at line 49 of file raminit.c.

◆ RCOMP_MMIO

#define RCOMP_MMIO ((u8 *)0x200000)

Definition at line 56 of file raminit.c.

◆ SLOW_DOWN_IO

#define SLOW_DOWN_IO inb(0x80)

Definition at line 172 of file raminit.c.

◆ SPD_ERROR

#define SPD_ERROR "Error reading SPD info\n"

Definition at line 46 of file raminit.c.

Enumeration Type Documentation

◆ d060_cc

enum d060_cc

Enumerator
D060_CMD_0
D060_CMD_1

Definition at line 195 of file raminit.c.

◆ mchtst_cc

enum mchtst_cc

Enumerator
MCHTST_CMD_0
D060_ENABLE
D060_DISABLE
RCOMP_BAR_ENABLE
RCOMP_BAR_DISABLE

Definition at line 187 of file raminit.c.

◆ rcomp_smr_cc

enum rcomp_smr_cc

Enumerator
RCOMP_HOLD
RCOMP_RELEASE
RCOMP_SMR_00
RCOMP_SMR_01

Definition at line 200 of file raminit.c.

Function Documentation

◆ are_spd_values_equal()

static uint8_t are_spd_values_equal	(	uint8_t	spd_byte_number,
		uint16_t	dimm0_address,
		uint16_t	dimm1_address
	)

static

Determine whether two DIMMs have the same value for an SPD parameter.

Parameters

spd_byte_number	The SPD byte number to compare in both DIMMs.
dimm0_address	SMBus address of the 1st DIMM socket to interrogate.
dimm1_address	SMBus address of the 2nd DIMM socket to interrogate.

Returns: 1 if both DIMM sockets report the same value for the specified SPD parameter, 0 if the values differed or an error occurred.

Definition at line 453 of file raminit.c.

References smbus_read_byte().

Referenced by spd_get_supported_dimms().

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◆ configure_dimm_row_boundaries()

static uint8_t configure_dimm_row_boundaries	(	struct dimm_size	dimm_log2_num_bits,
		uint8_t	total_dram_64M_multiple,
		unsigned int	dimm_index
	)

static

Configure the E7501's DRAM Row Boundary (DRB) registers for the memory present in the specified DIMM.

Parameters

dimm_log2_num_bits	Specifies log2(number of bits) for each side of the DIMM.
total_dram_64M_multiple	Total DRAM in the system (as a multiple of 64 MB) for DIMMs < dimm_index.
dimm_index	Which DIMM pair is being processed (0..MAX_DIMM_SOCKETS_PER_CHANNEL).

Returns: New multiple of 64 MB total DRAM in the system.

Definition at line 719 of file raminit.c.

References ASSERT, DRB_ROW_0, DRB_ROW_1, MAX_DIMM_SOCKETS_PER_CHANNEL, MCHDEV, pci_write_config8(), dimm_size::side1, and dimm_size::side2.

Referenced by configure_e7501_ram_addresses().

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◆ configure_e7501_cas_latency()

static void configure_e7501_cas_latency	(	const struct mem_controller *	ctrl,
		uint8_t	dimm_mask
	)

static

Determine the shortest CAS# latency that the E7501 and all DIMMs have in common, and program the E7501 to use it.

Parameters

ctrl	PCI addresses of memory controller functions, and SMBus addresses of DIMM slots on the mainboard.
dimm_mask	Bitmask of populated DIMMs, spd_get_supported_dimms().

Definition at line 1006 of file raminit.c.

References mem_controller::channel0, mem_controller::channel1, die(), DRA, dram_timing(), DRDCTL, DRT, DRT_CAS_2_0, DRT_CAS_2_5, DRT_CAS_MASK, log2(), MAX_DIMM_SOCKETS, MAX_DIMM_SOCKETS_PER_CHANNEL, MCHDEV, pci_read_config16(), pci_read_config32(), pci_write_config16(), pci_write_config32(), smbus_read_byte(), SPD_ACCEPTABLE_CAS_LATENCIES, SPD_CAS_LATENCY_2_0, SPD_CAS_LATENCY_2_5, SPD_ERROR, SPD_MIN_CYCLE_TIME_AT_CAS_MAX, SPD_SDRAM_CYCLE_TIME_2ND, SPD_SDRAM_CYCLE_TIME_3RD, and value.

Referenced by sdram_set_spd_registers().

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◆ configure_e7501_dram_controller_mode()

static void configure_e7501_dram_controller_mode	(	const struct mem_controller *	ctrl,
		uint8_t	dimm_mask
	)

static

Configure the refresh interval so that we refresh no more often than required by the "most needy" DIMM.

Also disable ECC if any of the DIMMs don't support it.

Parameters

ctrl	PCI addresses of memory controller functions, and SMBus addresses of DIMM slots on the mainboard.
dimm_mask	Bitmask of populated DIMMs, spd_get_supported_dimms().

Definition at line 1158 of file raminit.c.

References ASSERT, BIOS_ERR, mem_controller::channel0, mem_controller::channel1, die_on_spd_error(), DRC, ERROR_SCHEME_ECC, MAX_DIMM_SOCKETS, MAX_DIMM_SOCKETS_PER_CHANNEL, MAX_SPD_REFRESH_RATE, MCHDEV, pci_read_config32(), pci_write_config32(), printk, refresh_frequency, refresh_rate_map, smbus_read_byte(), SPD_DIMM_CONFIG_TYPE, SPD_REFRESH, and value.

Referenced by sdram_set_spd_registers().

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◆ configure_e7501_dram_timing()

static void configure_e7501_dram_timing	(	const struct mem_controller *	ctrl,
		uint8_t	dimm_mask
	)

static

Program the DRAM Timing register (DRT) of the E7501 (except for CAS# latency, which is assumed to have been programmed already), based on the parameters of the various installed DIMMs.

Parameters

ctrl	PCI addresses of memory controller functions, and SMBus addresses of DIMM slots on the mainboard.
dimm_mask	Bitmask of populated DIMMs, see spd_get_supported_dimms().

Definition at line 875 of file raminit.c.

References ASSERT, mem_controller::channel0, mem_controller::channel1, die(), dram_timing(), DRT, DRT_CAS_2_0, DRT_CAS_2_5, DRT_CAS_MASK, MAX_DIMM_SOCKETS, MAX_DIMM_SOCKETS_PER_CHANNEL, MCHDEV, pci_read_config32(), pci_write_config32(), smbus_read_byte(), SPD_ERROR, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY, SPD_MIN_RAS_TO_CAS_DELAY, SPD_MIN_ROW_PRECHARGE_TIME, and value.

Referenced by sdram_set_spd_registers().

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◆ configure_e7501_ram_addresses()

static void configure_e7501_ram_addresses	(	const struct mem_controller *	ctrl,
		uint8_t	dimm_mask
	)

static

Set the E7501's DRAM row boundary addresses & its Top Of Low Memory (TOLM).

If necessary, set up a remap window so we don't waste DRAM that ordinarily would lie behind addresses reserved for memory-mapped I/O.

Parameters

ctrl	PCI addresses of memory controller functions, and SMBus addresses of DIMM slots on the mainboard.
dimm_mask	Bitmask of populated DIMMs, see spd_get_supported_dimms().

Definition at line 782 of file raminit.c.

References AGPDEV, APSIZE, APSIZE1, mem_controller::channel0, configure_dimm_row_boundaries(), die(), DRB_ROW_0, DRB_ROW_4, GiB, MAX, MAX_DIMM_SOCKETS_PER_CHANNEL, MCHDEV, MiB, MIN, pci_read_config16(), pci_write_config16(), pci_write_config32(), pci_write_config8(), RAM_DEBUG_HEX32, RAM_DEBUG_MESSAGE, REMAPBASE, REMAPLIMIT, dimm_size::side1, dimm_size::side2, spd_get_dimm_size(), and TOLM.

Referenced by sdram_enable().

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◆ configure_e7501_row_attributes()

static void configure_e7501_row_attributes	(	const struct mem_controller *	ctrl,
		uint8_t	dimm_mask
	)

static

Configure the E7501's DRAM Row Attributes (DRA) registers based on DIMM parameters read via SPD.

This tells the controller the width of the SDRAM chips on each DIMM side (x4 or x8) and the page size of each DIMM side (4, 8, 16, or 32 KB).

Parameters

ctrl	PCI addresses of memory controller functions, and SMBus addresses of DIMM slots on the mainboard.
dimm_mask	Bitmask of populated DIMMs, spd_get_supported_dimms().

Definition at line 1248 of file raminit.c.

References mem_controller::channel0, DRA, MAX_DIMM_SOCKETS_PER_CHANNEL, MCHDEV, pci_write_config32(), sdram_spd_get_page_size(), sdram_spd_get_width(), dimm_size::side1, and dimm_size::side2.

Referenced by sdram_set_spd_registers().

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◆ d060_control()

static void d060_control ( d060_cc cmd )

static

Definition at line 249 of file raminit.c.

References D060_CMD_0, D060_CMD_1, D060_DISABLE, D060_ENABLE, D060DEV, mchtest_control(), pci_read_config32(), and pci_write_config32().

Referenced by ram_set_rcomp_regs(), and sdram_set_registers().

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◆ die_on_spd_error()

static void die_on_spd_error ( int spd_return_value )

static

Definition at line 293 of file raminit.c.

References die().

Referenced by configure_e7501_dram_controller_mode().

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◆ do_ram_command()

static void do_ram_command	(	uint8_t	command,
		uint16_t	jedec_mode_bits
	)

static

Send the specified command to all DIMMs.

Parameters

command	Specifies the command to be sent to the DIMMs.
jedec_mode_bits	For the MRS & EMRS commands, bits 0-12 contain the register value in JEDEC format.

Definition at line 611 of file raminit.c.

References ASSERT, DRB_ROW_0, DRC, EXTRA_DELAY, MAX_DIMM_SOCKETS_PER_CHANNEL, MAX_NUM_CHANNELS, MCHDEV, pci_read_config32(), pci_read_config8(), pci_write_config32(), RAM_COMMAND_EMRS, RAM_COMMAND_MRS, RAM_COMMAND_NORMAL, and read32().

Referenced by sdram_enable(), and set_ram_mode().

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◆ e7505_mch_is_ready()

static int e7505_mch_is_ready ( void )

static

Definition at line 1686 of file raminit.c.

References DRC, DRC_DONE, MCHDEV, and pci_read_config32().

Referenced by sdram_initialize().

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◆ enable_e7501_clocks()

static void enable_e7501_clocks ( uint8_t dimm_mask )

static

Definition at line 1297 of file raminit.c.

References CKDIS, clock_disable, MAX_DIMM_SOCKETS_PER_CHANNEL, MCHDEV, pci_read_config8(), and pci_write_config8().

Referenced by sdram_set_spd_registers().

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◆ local_udelay()

static void local_udelay ( int i )

static

Definition at line 173 of file raminit.c.

References SLOW_DOWN_IO.

◆ mchtest_control()

static void mchtest_control ( mchtst_cc cmd )

static

MCHTST - 0xF4 - 0xF7 – Based on similarity to 855PM.

[31:31] Purpose unknown [30:30] Purpose unknown [29:23] Unknown - not used? [22:22] System Memory MMR Enable 0 == Disable: mem space and BAR at 0x14 are not accessible 1 == Enable: mem space and BAR at 0x14 are accessible [21:20] Purpose unknown [19:02] Unknown - not used? [01:01] D6EN (Device #6 enable) 0 == Disable 1 == Enable [00:00] Unknown - not used?

Definition at line 223 of file raminit.c.

References D060_DISABLE, D060_ENABLE, MCHDEV, MCHTST, MCHTST_CMD_0, pci_read_config32(), pci_write_config32(), RCOMP_BAR_DISABLE, and RCOMP_BAR_ENABLE.

Referenced by d060_control(), and ram_set_rcomp_regs().

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◆ RAM_RESET_DDR_PTR()

static void RAM_RESET_DDR_PTR ( void )

static

DDR Receive FIFO RE-Sync (?)

Definition at line 1322 of file raminit.c.

References MCHDEV, pci_read_config8(), and pci_write_config8().

Referenced by sdram_enable(), and sdram_set_spd_registers().

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◆ ram_set_rcomp_regs()

static void ram_set_rcomp_regs ( void )

static

Definition at line 1442 of file raminit.c.

References D060_CMD_0, d060_control(), MCHDEV, mchtest_control(), MCHTST_CMD_0, pci_read_config8(), pci_write_config32(), RCOMP_BAR_DISABLE, RCOMP_BAR_ENABLE, rcomp_copy_registers(), RCOMP_HOLD, RCOMP_MMIO, RCOMP_RELEASE, RCOMP_SMR_00, RCOMP_SMR_01, rcomp_smr_control(), SLOW_DOWN_IO, and SMRBASE.

Referenced by sdram_set_registers().

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◆ rcomp_copy_registers()

static void rcomp_copy_registers ( void )

static

Set the E7501's (undocumented) RCOMP registers.

Per the 855PM datasheet and IXP2800 HW Initialization Reference Manual, RCOMP registers appear to affect drive strength, pullup/pulldown offset, and slew rate of various signal groups.

Comments below are conjecture based on apparent similarity between the E7501 and these two chips.

Definition at line 1360 of file raminit.c.

References CKESTR, CKSTR, CSBSTR, DQCMDSTR, pull_updown_offset_table, RAM_DEBUG_MESSAGE, RCOMP_MMIO, RCVENSTR, read32(), read8(), slew_2x, write16(), write32(), write8(), and write_8dwords().

Referenced by ram_set_rcomp_regs().

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◆ rcomp_smr_control()

static void rcomp_smr_control ( rcomp_smr_cc cmd )

static

Definition at line 268 of file raminit.c.

References RCOMP_HOLD, RCOMP_MMIO, RCOMP_RELEASE, RCOMP_SMR_00, RCOMP_SMR_01, read32(), SMRCTL, and write32().

Referenced by ram_set_rcomp_regs().

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◆ sdram_enable()

static void sdram_enable ( const struct mem_controller * ctrl )

static

Go through the JEDEC initialization sequence for all DIMMs, then enable refresh and initialize ECC and memory to zero.

Upon exit, SDRAM is up and running.

Parameters

ctrl	PCI addresses of memory controller functions, and SMBus addresses of DIMM slots on the mainboard.

Definition at line 1481 of file raminit.c.

References configure_e7501_ram_addresses(), DO_DELAY, do_ram_command(), DRC, E7501_SDRAM_MODE, EXTRA_DELAY, MCHDEV, pci_read_config16(), pci_read_config32(), pci_write_config32(), RAM_COMMAND_CBR, RAM_COMMAND_EMRS, RAM_COMMAND_NOP, RAM_COMMAND_NORMAL, RAM_COMMAND_PRECHARGE, RAM_DEBUG_MESSAGE, RAM_RESET_DDR_PTR(), SDRAM_EXTMODE_DLL_ENABLE, SDRAM_EXTMODE_DRIVE_NORMAL, SDRAM_MODE_DLL_RESET, SDRAM_MODE_NORMAL, set_ram_mode(), and SKPD.

Referenced by sdram_initialize().

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◆ sdram_initialize()

void sdram_initialize ( void )

Definition at line 1692 of file raminit.c.

References BIOS_DEBUG, mem_controller::d0, e7505_mch_is_ready(), PCI_DEV, printk, sdram_enable(), sdram_post_ecc(), sdram_set_registers(), sdram_set_spd_registers(), timestamp_add_now(), TS_INITRAM_END, and TS_INITRAM_START.

Referenced by mainboard_romstage_entry(), and perform_raminit().

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◆ sdram_post_ecc()

static void sdram_post_ecc ( const struct mem_controller * ctrl )

static

Parameters

ctrl	PCI addresses of memory controller functions, and SMBus addresses of DIMM slots on the mainboard.

Definition at line 1560 of file raminit.c.

References DRC, MCHDEV, pci_read_config32(), and pci_write_config32().

Referenced by sdram_initialize().

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◆ sdram_set_registers()

static void sdram_set_registers ( const struct mem_controller * ctrl )

static

Do basic RAM setup that does NOT depend on serial presence detect information (i.e.

independent of DIMM specifics).

Parameters

ctrl	PCI addresses of memory controller functions, and SMBus addresses of DIMM slots on the mainboard.

Definition at line 1622 of file raminit.c.

References CKDIS, D060_CMD_1, d060_control(), DRA, DRB_ROW_0, DRB_ROW_4, DRC, DRT, DVNP, MCHDEV, PAM_0, pci_read_config16(), pci_read_config32(), pci_read_config8(), pci_write_config16(), pci_write_config32(), pci_write_config8(), ram_set_rcomp_regs(), REMAPBASE, REMAPLIMIT, TOLM, and word.

Referenced by sdram_initialize().

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◆ sdram_set_spd_registers()

static void sdram_set_spd_registers ( const struct mem_controller * ctrl )

static

Configure SDRAM controller parameters that depend on characteristics of the DIMMs installed in the system.

These characteristics are read from the DIMMs via the standard Serial Presence Detect (SPD) interface.

Parameters

ctrl	PCI addresses of memory controller functions, and SMBus addresses of DIMM slots on the mainboard.

Definition at line 1577 of file raminit.c.

References BIOS_DEBUG, configure_e7501_cas_latency(), configure_e7501_dram_controller_mode(), configure_e7501_dram_timing(), configure_e7501_row_attributes(), DO_DELAY, enable_e7501_clocks(), MCHDEV, pci_write_config16(), printk, RAM_DEBUG_MESSAGE, RAM_RESET_DDR_PTR(), SKPD, and spd_get_supported_dimms().

Referenced by sdram_initialize().

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◆ sdram_spd_get_page_size()

static struct dimm_size sdram_spd_get_page_size ( uint16_t dimm_socket_address )

static

Calculate the page size for each physical bank of the DIMM: log2(page size) = (# columns) + log2(data width)

NOTE: Page size is the total number of data bits in a row.

Parameters

dimm_socket_address SMBus address of DIMM socket to interrogate.

Returns: log2(page size) for each side of the DIMM.

Definition at line 293 of file raminit.c.

Referenced by configure_e7501_row_attributes(), and spd_get_supported_dimms().

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◆ sdram_spd_get_width()

static struct dimm_size sdram_spd_get_width ( uint16_t dimm_socket_address )

static

Read the width in bits of each DIMM side's DRAMs via SPD (i.e.

4, 8, 16).

Parameters

dimm_socket_address SMBus address of DIMM socket to interrogate.

Returns: Width in bits of each DIMM side's DRAMs.

Definition at line 293 of file raminit.c.

Referenced by configure_e7501_row_attributes(), and spd_get_supported_dimms().

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◆ set_ram_mode()

static void set_ram_mode ( uint16_t jedec_mode_bits )

static

Set the mode register of all DIMMs.

The proper CAS# latency setting is added to the mode bits specified by the caller.

Parameters

jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the register value in JEDEC format.

Definition at line 679 of file raminit.c.

References ASSERT, BUG, do_ram_command(), DRT, DRT_CAS_2_0, DRT_CAS_2_5, DRT_CAS_MASK, MCHDEV, pci_read_config32(), RAM_COMMAND_MRS, SDRAM_CAS_2_0, SDRAM_CAS_2_5, and SDRAM_CAS_MASK.

Referenced by sdram_enable().

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◆ spd_get_dimm_size()

static struct dimm_size spd_get_dimm_size ( unsigned int dimm_socket_address )

static

Calculate the log base 2 size in bits of both DIMM sides.

log2(# bits) = (# columns) + log2(data width) + (# rows) + log2(banks per SDRAM)

Note that it might be easier to use SPD byte 31 here, it has the DIMM size as a multiple of 4MB. The way we do it now we can size both sides of an asymmetric DIMM.

Parameters

dimm_socket_address SMBus address of DIMM socket to interrogate.

Returns: log2(number of bits) for each side of the DIMM.

Definition at line 293 of file raminit.c.

Referenced by configure_e7501_ram_addresses().

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◆ spd_get_supported_dimms()

static uint8_t spd_get_supported_dimms ( const struct mem_controller * ctrl )

static

Scan for compatible DIMMs.

The code in this module only supports dual-channel operation, so we test that compatible DIMMs are paired.

Parameters

ctrl	PCI addresses of memory controller functions, and SMBus addresses of DIMM slots on the mainboard.

Returns: A bitmask indicating which of the possible sockets for each channel was found to contain a compatible DIMM. Bit 0 corresponds to the closest socket for channel 0 Bit 1 to the next socket for channel 0 ... Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0 Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1 ... Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1

Definition at line 486 of file raminit.c.

References are_spd_values_equal(), ASSERT, BIOS_DEBUG, mem_controller::channel0, mem_controller::channel1, dual_channel_parameters, MAX_DIMM_SOCKETS_PER_CHANNEL, MODULE_REGISTERED, printk, sdram_spd_get_page_size(), sdram_spd_get_width(), dimm_size::side1, dimm_size::side2, smbus_read_byte(), SPD_BURST_LENGTH_4, SPD_MEMORY_TYPE, SPD_MEMORY_TYPE_SDRAM_DDR, SPD_MODULE_ATTRIBUTES, SPD_MODULE_VOLTAGE, SPD_SUPPORTED_BURST_LENGTHS, and SPD_VOLTAGE_SSTL2.

Referenced by sdram_set_spd_registers().

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◆ write_8dwords()

static void write_8dwords	(	const uint32_t *	src_addr,
		u8 *	dst_addr
	)

static

Copy 64 bytes from one location to another.

Parameters

src_addr	TODO
dst_addr	TODO

Definition at line 1340 of file raminit.c.

References write32().

Referenced by rcomp_copy_registers().

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Variable Documentation

◆ dual_channel_parameters

const uint8_t dual_channel_parameters[]

static

Initial value:

= {
        SPD_MEMORY_TYPE,
        SPD_MODULE_VOLTAGE,
        SPD_NUM_COLUMNS,
        SPD_NUM_ROWS,
        SPD_NUM_DIMM_BANKS,
        SPD_PRIMARY_SDRAM_WIDTH,
        SPD_NUM_BANKS_PER_SDRAM
}

Definition at line 98 of file raminit.c.

Referenced by spd_get_supported_dimms().

◆ pull_updown_offset_table

const uint32_t pull_updown_offset_table[]

static

Initial value:

= {
        0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
        0x88888888, 0x88888888, 0x88888888, 0x88888888,
}

Definition at line 162 of file raminit.c.

Referenced by rcomp_copy_registers().

◆ refresh_frequency

const uint32_t refresh_frequency[]

static

Initial value:

= {
        
        0, 2, 3, 1, 0, 0, 0, 4
}

Definition at line 63 of file raminit.c.

Referenced by configure_e7501_dram_controller_mode().

◆ refresh_rate_map

const uint32_t refresh_rate_map[]

static

Initial value:

= {
        
        1, 7, 2, 1, 1, 3
}

Definition at line 79 of file raminit.c.

Referenced by configure_e7501_dram_controller_mode().

◆ slew_2x

const uint32_t slew_2x[]

static

Initial value:

= {
        0x00000000, 0x76543210, 0xffffeca8, 0xffffffff,
        0x21000000, 0xa8765432, 0xffffffec, 0xffffffff,
}

Definition at line 156 of file raminit.c.

Referenced by rcomp_copy_registers().

Data Structures

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

◆ AGPDEV

◆ D060DEV

◆ DO_DELAY

◆ E7501_SDRAM_MODE

◆ EXTRA_DELAY

◆ MAX_SPD_REFRESH_RATE

◆ MCHDEV

◆ RAM_DEBUG_HEX32

◆ RAM_DEBUG_HEX8

◆ RAM_DEBUG_MESSAGE

◆ RASDEV

◆ RCOMP_MMIO

◆ SLOW_DOWN_IO

◆ SPD_ERROR

Enumeration Type Documentation

◆ d060_cc

◆ mchtst_cc

◆ rcomp_smr_cc

Function Documentation

◆ are_spd_values_equal()

◆ configure_dimm_row_boundaries()

◆ configure_e7501_cas_latency()

◆ configure_e7501_dram_controller_mode()

◆ configure_e7501_dram_timing()

◆ configure_e7501_ram_addresses()

◆ configure_e7501_row_attributes()

◆ d060_control()

◆ die_on_spd_error()

◆ do_ram_command()

◆ e7505_mch_is_ready()

◆ enable_e7501_clocks()

◆ local_udelay()

◆ mchtest_control()

◆ RAM_RESET_DDR_PTR()

◆ ram_set_rcomp_regs()

◆ rcomp_copy_registers()

◆ rcomp_smr_control()

◆ sdram_enable()

◆ sdram_initialize()

◆ sdram_post_ecc()

◆ sdram_set_registers()

◆ sdram_set_spd_registers()

◆ sdram_spd_get_page_size()

◆ sdram_spd_get_width()

◆ set_ram_mode()

◆ spd_get_dimm_size()

◆ spd_get_supported_dimms()

◆ write_8dwords()

Variable Documentation

◆ dual_channel_parameters

◆ pull_updown_offset_table

◆ refresh_frequency

◆ refresh_rate_map

◆ slew_2x