3 #ifndef __SOC_NVIDIA_TEGRA210_CLOCK_H__
4 #define __SOC_NVIDIA_TEGRA210_CLOCK_H__
9 #include <soc/clk_rst.h>
182 #define CLK_SRC_DEV_ID(dev, src) CLK_SRC_##dev##_##src
183 #define CLK_SRC_FREQ_ID(dev, src) CLK_SRC_FREQ_##dev##_##src
185 #define CLK_SRC_DEVICE(dev, a, b, c, d, e, f, g, h) \
186 CLK_SRC_DEV_ID(dev, a) = 0, \
187 CLK_SRC_DEV_ID(dev, b) = 1, \
188 CLK_SRC_DEV_ID(dev, c) = 2, \
189 CLK_SRC_DEV_ID(dev, d) = 3, \
190 CLK_SRC_DEV_ID(dev, e) = 4, \
191 CLK_SRC_DEV_ID(dev, f) = 5, \
192 CLK_SRC_DEV_ID(dev, g) = 6, \
193 CLK_SRC_DEV_ID(dev, h) = 7, \
194 CLK_SRC_FREQ_ID(dev, a) = a, \
195 CLK_SRC_FREQ_ID(dev, b) = b, \
196 CLK_SRC_FREQ_ID(dev, c) = c, \
197 CLK_SRC_FREQ_ID(dev, d) = d, \
198 CLK_SRC_FREQ_ID(dev, e) = e, \
199 CLK_SRC_FREQ_ID(dev, f) = f, \
200 CLK_SRC_FREQ_ID(dev, g) = g, \
201 CLK_SRC_FREQ_ID(dev, h) = h
251 #define CLOCK_PLL_STABLE_DELAY_US 300
253 #define IO_STABILIZATION_DELAY (2)
254 #define LOGIC_STABILIZATION_DELAY (2)
277 #define CLK_DIVIDER(REF, FREQ) (DIV_ROUND_UP(((REF) * 2), (FREQ)) - 2)
296 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / ((REG) + 2))
304 if (div & ~div_mask) {
312 #define get_i2c_clk_div(src, freq) \
313 (DIV_ROUND_UP(src, (freq) * (0x19 + 1) * 8) - 1)
314 #define get_clk_div(src,freq) CLK_DIVIDER(src,freq)
315 #define CLK_DIV_MASK 0xff
316 #define CLK_DIV_MASK_I2C 0xffff
318 #define clock_configure_source(device, src, freq) \
319 _clock_set_div(CLK_RST_REG(clk_src_##device), #device, \
320 get_clk_div(TEGRA_##src##_KHZ, freq), CLK_DIV_MASK, \
321 CLK_SRC_DEV_ID(device, src))
324 #define TEGRA_CLK_M_KHZ (clock_get_osc_khz()/2)
325 #define TEGRA_PLLX_KHZ CONFIG_PLLX_KHZ
326 #define TEGRA_PLLP_KHZ (408000)
327 #define TEGRA_PLLP_OUT3_KHZ (68000)
328 #define TEGRA_PLLC_KHZ (600000)
329 #define TEGRA_PLLD_KHZ (925000)
330 #define TEGRA_PLLD_OUT0_KHZ (TEGRA_PLLD_KHZ/2)
331 #define TEGRA_PLLU_KHZ (960000)
333 #define clock_enable(l, h, u, v, w, x, y) \
335 u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x, y}; \
336 clock_enable_regs(bits); \
339 #define clock_disable(l, h, u, v, w, x, y) \
341 u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x, y}; \
342 clock_disable_regs(bits); \
345 #define clock_set_reset(l, h, u, v, w, x, y) \
347 u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x, y}; \
348 clock_set_reset_regs(bits); \
351 #define clock_clr_reset(l, h, u, v, w, x, y) \
353 u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x, y}; \
354 clock_clr_reset_regs(bits); \
357 #define clock_enable_l(l) clock_enable(l, 0, 0, 0, 0, 0, 0)
358 #define clock_enable_h(h) clock_enable(0, h, 0, 0, 0, 0, 0)
359 #define clock_enable_u(u) clock_enable(0, 0, u, 0, 0, 0, 0)
360 #define clock_enable_v(v) clock_enable(0, 0, 0, v, 0, 0, 0)
361 #define clock_enable_w(w) clock_enable(0, 0, 0, 0, w, 0, 0)
362 #define clock_enable_x(x) clock_enable(0, 0, 0, 0, 0, x, 0)
363 #define clock_enable_y(y) clock_enable(0, 0, 0, 0, 0, 0, y)
365 #define clock_disable_l(l) clock_disable(l, 0, 0, 0, 0, 0, 0)
366 #define clock_disable_h(h) clock_disable(0, h, 0, 0, 0, 0, 0)
367 #define clock_disable_u(u) clock_disable(0, 0, u, 0, 0, 0, 0)
368 #define clock_disable_v(v) clock_disable(0, 0, 0, v, 0, 0, 0)
369 #define clock_disable_w(w) clock_disable(0, 0, 0, 0, w, 0, 0)
370 #define clock_disable_x(x) clock_disable(0, 0, 0, 0, 0, x, 0)
371 #define clock_disable_y(y) clock_disable(0, 0, 0, 0, 0, 0, y)
373 #define clock_set_reset_l(l) clock_set_reset(l, 0, 0, 0, 0, 0, 0)
374 #define clock_set_reset_h(h) clock_set_reset(0, h, 0, 0, 0, 0, 0)
375 #define clock_set_reset_u(u) clock_set_reset(0, 0, u, 0, 0, 0, 0)
376 #define clock_set_reset_v(v) clock_set_reset(0, 0, 0, v, 0, 0, 0)
377 #define clock_set_reset_w(w) clock_set_reset(0, 0, 0, 0, w, 0, 0)
378 #define clock_set_reset_x(x) clock_set_reset(0, 0, 0, 0, 0, x, 0)
379 #define clock_set_reset_y(x) clock_set_reset(0, 0, 0, 0, 0, y, 0)
381 #define clock_clr_reset_l(l) clock_clr_reset(l, 0, 0, 0, 0, 0, 0)
382 #define clock_clr_reset_h(h) clock_clr_reset(0, h, 0, 0, 0, 0, 0)
383 #define clock_clr_reset_u(u) clock_clr_reset(0, 0, u, 0, 0, 0, 0)
384 #define clock_clr_reset_v(v) clock_clr_reset(0, 0, 0, v, 0, 0, 0)
385 #define clock_clr_reset_w(w) clock_clr_reset(0, 0, 0, 0, w, 0, 0)
386 #define clock_clr_reset_x(x) clock_clr_reset(0, 0, 0, 0, 0, x, 0)
387 #define clock_clr_reset_y(y) clock_clr_reset(0, 0, 0, 0, 0, 0, y)
389 #define clock_enable_clear_reset_l(l) \
390 clock_enable_clear_reset(l, 0, 0, 0, 0, 0, 0)
391 #define clock_enable_clear_reset_h(h) \
392 clock_enable_clear_reset(0, h, 0, 0, 0, 0, 0)
393 #define clock_enable_clear_reset_u(u) \
394 clock_enable_clear_reset(0, 0, u, 0, 0, 0, 0)
395 #define clock_enable_clear_reset_v(v) \
396 clock_enable_clear_reset(0, 0, 0, v, 0, 0, 0)
397 #define clock_enable_clear_reset_w(w) \
398 clock_enable_clear_reset(0, 0, 0, 0, w, 0, 0)
399 #define clock_enable_clear_reset_x(x) \
400 clock_enable_clear_reset(0, 0, 0, 0, 0, x, 0)
401 #define clock_enable_clear_reset_y(y) \
402 clock_enable_clear_reset(0, 0, 0, 0, 0, 0, y)
414 u32 stable_time,
u32 emc_source,
u32 same_freq);
423 u32 *rst_dev_clr_reg);
static __always_inline void hlt(void)
#define printk(level,...)
#define clrsetbits32(addr, clear, set)
#define BIOS_ERR
BIOS_ERR - System in incomplete state.
int clock_get_pll_input_khz(void)
void clock_reset_h(u32 h)
void clock_external_output(int clk_id)
void clock_halt_avp(void)
void sor_clock_stop(void)
void clock_reset_w(u32 w)
int clock_get_osc_khz(void)
void clock_early_uart(void)
void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, u32 same_freq)
void clock_reset_x(u32 x)
void sor_clock_start(void)
void clock_cpu0_config(void *entry)
void clock_reset_l(u32 l)
void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x)
void clock_reset_u(u32 u)
void clock_init_arm_generic_timer(void)
void clock_reset_v(u32 v)
static void _clock_set_div(u32 *reg, const char *name, u32 div, u32 div_mask, u32 src)
void clock_enable_audio(void)
void clock_disable_regs(u32 bits[DEV_CONFIG_BLOCKS])
void clock_set_reset_regs(u32 bits[DEV_CONFIG_BLOCKS])
u32 clock_configure_plld(u32 frequency)
void clock_clr_reset_regs(u32 bits[DEV_CONFIG_BLOCKS])
#define CLK_SRC_DEVICE(dev, a, b, c, d, e, f, g, h)
@ CLK_X_UART_FST_MIPI_CAL
void clock_reset_y(u32 y)
void clock_grp_enable_clear_reset(u32 val, u32 *clk_enb_set_reg, u32 *rst_dev_clr_reg)
void clock_enable_regs(u32 bits[DEV_CONFIG_BLOCKS])
#define m(clkreg, src_bits, pmcreg, dst_bits)
#define DEV_CONFIG_BLOCKS