coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
sram.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <device/device.h>
4 #include <device/pci.h>
5 #include <device/pci_ids.h>
6 #include <intelblocks/sram.h>
7 #include <soc/iomap.h>
8 
9 __weak void soc_sram_init(struct device *dev) { /* no-op */ }
10 
11 static void sram_read_resources(struct device *dev)
12 {
13  struct resource *res;
15 
16  res = new_resource(dev, PCI_BASE_ADDRESS_0);
17  res->base = SRAM_BASE_0;
18  res->size = SRAM_SIZE_0;
20 
21  res = new_resource(dev, PCI_BASE_ADDRESS_2);
22  res->base = SRAM_BASE_2;
23  res->size = SRAM_SIZE_2;
25 }
26 
27 static const struct device_operations device_ops = {
29  .set_resources = pci_dev_set_resources,
30  .enable_resources = pci_dev_enable_resources,
31  .init = soc_sram_init,
32  .ops_pci = &pci_dev_ops_pci,
33 };
34 
35 static const unsigned short pci_device_ids[] = {
52  0,
53 };
54 
55 static const struct pci_driver sram __pci_driver = {
56  .ops = &device_ops,
57  .vendor = PCI_VID_INTEL,
58  .devices = pci_device_ids,
59 };
struct resource * new_resource(struct device *dev, unsigned int index)
See if a resource structure already exists for a given index and if not allocate one.
Definition: device_util.c:346
#define SRAM_BASE_0
Definition: iomap.h:30
#define SRAM_SIZE_0
Definition: iomap.h:31
#define SRAM_SIZE_2
Definition: iomap.h:33
#define SRAM_BASE_2
Definition: iomap.h:32
#define PCI_BASE_ADDRESS_2
Definition: pci_def.h:65
#define PCI_BASE_ADDRESS_0
Definition: pci_def.h:63
void pci_dev_enable_resources(struct device *dev)
Definition: pci_device.c:721
void pci_dev_read_resources(struct device *dev)
Definition: pci_device.c:534
struct pci_operations pci_dev_ops_pci
Default device operation for PCI devices.
Definition: pci_device.c:911
void pci_dev_set_resources(struct device *dev)
Definition: pci_device.c:691
#define PCI_DID_INTEL_MTL_CRASHLOG_SRAM
Definition: pci_ids.h:4429
#define PCI_DID_INTEL_JSP_SRAM
Definition: pci_ids.h:4175
#define PCI_DID_INTEL_MTL_IOE_P_SRAM
Definition: pci_ids.h:4178
#define PCI_DID_INTEL_ADP_N_PMC_CRASHLOG_SRAM
Definition: pci_ids.h:4427
#define PCI_DID_INTEL_ADP_P_PMC_CRASHLOG_SRAM
Definition: pci_ids.h:4426
#define PCI_DID_INTEL_MTL_IOE_M_SRAM
Definition: pci_ids.h:4177
#define PCI_DID_INTEL_ICL_SRAM
Definition: pci_ids.h:4170
#define PCI_DID_INTEL_MCC_SRAM
Definition: pci_ids.h:4174
#define PCI_DID_INTEL_GLK_SRAM
Definition: pci_ids.h:4167
#define PCI_DID_INTEL_APL_SRAM
Definition: pci_ids.h:4166
#define PCI_DID_INTEL_CMP_H_SRAM
Definition: pci_ids.h:4172
#define PCI_VID_INTEL
Definition: pci_ids.h:2157
#define PCI_DID_INTEL_ADP_S_PMC_CRASHLOG_SRAM
Definition: pci_ids.h:4425
#define PCI_DID_INTEL_MTL_SOC_SRAM
Definition: pci_ids.h:4176
#define PCI_DID_INTEL_TGP_PMC_CRASHLOG_SRAM
Definition: pci_ids.h:4428
#define PCI_DID_INTEL_TGL_H_SRAM
Definition: pci_ids.h:4173
#define PCI_DID_INTEL_CMP_SRAM
Definition: pci_ids.h:4171
#define IORESOURCE_MEM
Definition: resource.h:10
#define IORESOURCE_ASSIGNED
Definition: resource.h:34
#define IORESOURCE_FIXED
Definition: resource.h:36
const struct smm_save_state_ops *legacy_ops __weak
Definition: save_state.c:8
static const struct pci_driver sram __pci_driver
Definition: sram.c:55
static const struct device_operations device_ops
Definition: sram.c:27
__weak void soc_sram_init(struct device *dev)
Definition: sram.c:9
static const unsigned short pci_device_ids[]
Definition: sram.c:35
static void sram_read_resources(struct device *dev)
Definition: sram.c:11
void(* read_resources)(struct device *dev)
Definition: device.h:39
Definition: device.h:107
unsigned long flags
Definition: resource.h:49
resource_t base
Definition: resource.h:45
resource_t size
Definition: resource.h:46